Circuit interface synchronization using slave variable delay loop

An apparatus for synchronizing clock signals comprising:

• a phase aligning circuit coupled to receive a reference clock signal and generate an output signal, which is phase aligned with the reference clock signal;
• a fixed delay circuit coupled to the phase aligning circuit to receive its output signal and for generating a first clock signal, which is delayed from the output signal by a first delay interval;
• the first clock signal coupled to a first destination and also coupled as feedback to the phase aligning circuit;
• a slave circuit coupled to receive the output signal of the phase aligning circuit and for generating a second clock signal to a second destination, wherein the second clock signal is delayed from the output signal by a second delay interval;
• the slave circuit also coupled to receive the reference clock signal to detect a phase difference between the reference clock signal and the second clock signal and adjusting the second delay to synchronize the first and second clock signals.

An apparatus for synchronizing clock signals comprising:

• a phase aligning circuit coupled to receive a first reference clock signal and generate a reference output signal, which is phase aligned with the first reference clock signal;
• a fixed delay circuit coupled to the phase aligning circuit to receive its reference output signal and for generating a first clock output signal, which is delayed from the reference output signal by a first delay interval;
• the first clock output signal also coupled as feedback to the phase aligning circuit;
• a slave circuit coupled to receive the reference output signal of the phase aligning circuit and for generating a second clock output signal, wherein the second clock output signal is delayed from the reference output signal by a second delay interval;
• the slave circuit also coupled to receive a second reference clock signal to detect a phase difference between the second reference clock signal and the second clock output signal and adjusting the second delay interval to synchronize the first and second clock output signals.

An apparatus for synchronizing clock signals comprising:

• means for aligning the phases of a first clock output signal with a first reference clock signal;
• means for receiving an output from the means for aligning and delaying the first reference clock signal by a first delay interval to generate the first clock output signal;
• means for variably delaying the output from the means for aligning by a second delay interval to generate a second clock output signal;
• and
• means for determining a phase difference between the second clock output signal and a second reference clock signal to vary the second delay interval to synchronize the first and second clock output signals.