Method and apparatus for using function context to improve branch
AssigneeIntel Corporation
InventorRichard Malizewski
Life of this patent
Estimating the term…
Abstract
An apparatus for predicting branch behavior during execution of branch instructions in a computer program. The apparatus comprises a branch table buffer (BTB) to store a plurality of branch addresses that are each generated during a function call and a plurality of branch histories associated with the branch addresses, the branch histories indicating whether or not an associated branch was previously taken. The apparatus further comprises circuitry coupled to the BTB to generate an index into the BTB using at least one level of context of the function call.
Claims20
An apparatus for predicting branch behavior during execution of branch instructions in a computer program, comprising:
- a branch table buffer (BTB) to store a plurality of branch addresses that are each generated during a function call and a plurality of branch histories associated with the branch addresses, the branch histories indicating whether or not an associated branch was previously taken;
- and
- circuitry coupled to the BTB to generate an index into the BTB for any type of branch using selected bits of a current branch address and at least one selected bit of a pending return address of a function call.
A method for predicting branch behavior in the execution of a computer program, comprising the steps of:
- storing a plurality of branch addresses in a branch table buffer (BTB), wherein each branch address is generated during a function call;
- storing a plurality of branch histories associated with the branch addresses in the branch table buffer (BTB), wherein the branch histories indicate whether or not an associated branch was previously taken;
- and
- generating an index into the BTB for any type of branch using selected bits of a current branch address and at least one selected bit of a pending return address of the function call.
An apparatus for reducing a number of mispredicted branches in a processor that executes branch instructions of a computer program, comprising:
- a branch table buffer (BTB) to store a plurality of branch addresses each associated with a branch instruction of the computer program, and a history associated with each of the plurality of branch addresses;
- a first storage device to store a pending return address associated with a context of the branch instruction;
- a second storage device to store the current branch address;
- and an index generation circuit coupled to the first and second storage devices to generate an index into the BTB for any type of branch using selected bits of the current branch address and at least one selected bit of the pending return address.
Dependencies are inferred from the claim text.