Instruction fetch mechanism with simultaneous prediction of control-flow instructions

An instruction fetch unit that concurrently makes multiple predictions for different types of branches comprising:

• a branch address table configured to store predicted branch target addresses for branch instructions and to output a predicted branch target address signal;
• a sequential address circuit configured to calculate a sequential address and to output a sequential fetch address signal;
• a return address unit configured to store a return address for a call instruction and configured to output a return address signal;
• a branch misprediction recovery circuit configured to store a corrected branch target address for a mispredicted branch instruction and to output a corrected branch target address signal;
• a multiplexer coupled to receive a plurality of input signals including said predicted branch target address signal, said sequential fetch address signal, said return address signal and said corrected branch target address signal, and configured to output a fetch bundle address signal that addresses a fetch bundle;
• a branch predictor coupled to said fetch bundle address signal and said branch logic circuit, wherein said branch predictor predicts whether conditional branches within said fetch bundle are taken or not taken
• a branch logic circuit coupled to a control signal of said multiplexer, wherein said branch logic circuit is configured to cause said multiplexer to select one of said plurality of input signals in dependence on the occurrence of a control-flow instruction within said fetch bundle or the occurrence of a mispredicted branch instruction;
• a predecode circuit configured to generate an array of predecode bits that identifies a type of instructions with said fetch bundle, wherein said branch logic circuit is configured to use said array of predecode bits to identify the occurrence and location of branch instructions.

An instruction fetch unit that concurrently makes multiple predictions for different types of control-flow instructions comprising:

• a branch address table configured to store predicted branch target addresses for branch instructions and to output two predicted branch target address signals;
• a sequential address circuit configured to calculate a sequential address and to output a sequential fetch address signal;
• an unresolved branch circuit configured to store a corrected branch target address for a mispredicted branch instruction and to output a corrected branch target address signal;
• a multiplexer coupled to receive a plurality of input signals including said predicted branch target address signal, said sequential fetch address signal and said corrected branch target address signal, and configured to output a current fetch bundle address signal that addresses a fetch bundle;
• and
• a branch logic circuit coupled to provide a control signal to said multiplexer, wherein said branch logic circuit is configured to cause said multiplexer to select one of said plurality of input signals in dependence on an occurrence of a control-flow instruction within said fetch bundle or an occurrence of a mispredicted branch instruction;
• wherein said branch address table is configured to output said two predicted branch target address signals to said multiplexer for each fetch bundle, and said branch logic circuit is configured to cause said multiplexer to select one of said two predicted branch target address signals in dependence on a location of a first unconditional branch instruction or a first taken conditional branch instruction within said fetch bundle.