Method and apparatus for implementing a speculative return stack buffer
AssigneeIntel Corporation
InventorsSimcha Gochman, Nicolas Kacevas, Farah Jubran
Life of this patent
Estimating the term…
Abstract
A return stack buffer mechanism that uses two separate return stack buffers is disclosed. The first return stack buffer is the Speculative Return Stack Buffer. The Speculative Return Stack Buffer is updated using speculatively fetched instructions. Thus, the Speculative Return Stack Buffer may become corrupted when incorrect instructions are fetched. The second return stack buffer is the Actual Return Stack Buffer. The Actual Return Stack Buffer is updated using information from fully executed branch instructions. When a branch misprediction causes a pipeline flush, the contents of the Actual Return Stack Buffer is copied into the Speculative Return Stack Buffer to correct any corrupted information.
Claims17
An apparatus for predicting return addresses for Return From Subroutine instructions, said apparatus comprising:
- a speculative return stack buffer, said speculative return stack buffer comprising a plurality of branch entries for storing information about a plurality of speculatively fetched branch instructions;
- an actual return stack buffer, said actual return stack buffer comprising a plurality of branch entries for storing information about a plurality of fully executed branch instructions;
- and
- a copy signal, said copy signal asserted when a pipeline flush occurs, and when said copy signal is asserted then said information about said plurality of fully executed branch instructions is copied into said speculative return stack buffer.
An apparatus for processing computer instructions, said apparatus comprising:
- a branch prediction circuit, said branch prediction circuit comprising:
- a branch target buffer cache for predicting branch instructions and branch target addresses for said branch instructions;
- a speculative return stack buffer, said speculative return stack buffer comprising a plurality of branch entries for storing information about a plurality of speculatively fetched branch instructions;
- an actual return stack buffer, said actual return stack buffer comprising a plurality of branch entries for storing information about a plurality of fully executed branch instructions;
- and
- a copy signal, said copy signal asserted when a pipeline flush occurs, and when said copy signal is asserted then said information about said plurality of fully executed branch instructions is copied into said speculative return stack buffer;
- an instruction fetch unit, said instruction fetch unit for fetching computer instructions;
- an execution unit, said execution unit for executing computer instructions;
- and
- a write results stage, said write results stage for writing results of fully executed computer instructions and for handling mispredictions of said speculatively fetched branch instructions.
A method for processing branch instructions, said method comprising:
- predicting branch instructions with a branch target buffer;
- updating a speculative return stack buffer comprising a plurality of branch entries with information from said predicted branch instructions;
- decoding each processor instruction to determine instruction type;
- executing said branch instructions;
- updating an actual return stack buffer comprising a plurality of branch entries with information about said executed branch instructions;
- verifying final branch target address of each said branch instructions with predicted target address;
- and
- copying said information about said executed branch instructions in said actual return stack buffer into said speculative return stack buffer when a pipeline flush occurs.
Dependencies are inferred from the claim text.