Method and apparatus for providing pipe fullness information external to a data processing system

A data processor, comprising:

• external bus interface circuitry;
• and
• a central processing unit, wherein the central processing unit comprises:
• an instruction pipe for storing a plurality of instructions in a serially connected set of instruction registers where contents of at least one of the serially connected set of instruction registers may be shifted to another of the serially connected set of instruction registers;
• a microsequencer, coupled to said instruction pipe, for receiving at least one of the plurality of instructions in a serial manner from the serially connected set of instruction registers;
• an execution unit, coupled to said microsequencer, for executing the at least one of the plurality of instructions;
• a fetch pointer circuit, coupled to said external bus interface circuitry for receiving at least one control signal indicating when said instruction pipe is loaded, and coupled to said microsequencer for receiving at least one control signal indicating when said instruction pipe is unloaded;
• and
• pipe tracking circuitry, coupled to said fetch pointer circuit and to said external bus interface circuitry, said pipe tracking circuitry providing a pipe status signal external to the data processor by way of said external bus interface circuitry, the pipe status signal indicating how many of the plurality of instructions are stored in the serially connected set of instruction registers of said instruction pipe.

A method for operating a data processing system, the data processing system having a central processing unit and having an external bus having a plurality of integrated circuit terminals, the external bus providing information external to the data processing system, the method comprising the steps of:

• providing an instruction pipe in the central processing unit;
• executing a plurality of instructions in the central processing unit from the instruction pipe;
• providing first status information on the external bus, wherein the first status information indicates a fullness level of the instruction pipe;
• and
• when the central processing unit is in a loop mode of operation, disabling subsequent toggling of the plurality of integrated circuit terminals for a period of time during the loop mode of operation.

A data processor comprising:

• a CPU having access to an instruction pipe containing a plurality of instruction registers, the instruction pipe being coupled to store instructions for execution by the CPU;
• and
• pipe tracking circuitry coupled to the instruction pipe for monitoring a status of the pipe over time and providing such status external to the CPU via external terminals of the CPU, the pipe tracking circuitry having:
• (1) a first external terminal for providing first pipe status information external to the CPU;
• (2) a second external terminal for providing second pipe status information external to the CPU;
• and (3) a third external terminal for providing third pipe status information external to the CPU.