US 5,964,857 AGranted

Priority encoder for a content addressable memory system

AssigneeQuality Semiconductor, Inc.

InventorsVaradarajan Srinivasan, Ketan K. Mehta, Sanjay V. Gala, Ruchir P. Shah

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Abstract

A priority encoder for generating a priority-encoded address which identifies the highest priority request line. According to one priority scheme, the active request line having the lowest address has the highest priority. The priority encoder is capable of generating the priority-encoded address by determining information corresponding to the most significant bits of the priority-encoded address and using this information in the computation of less significant bits of the priority-encoded address. Using purely combinatorial logic, including switch elements, the priority encoder is capable of computing lower order bits using feedback signals resulting from the computation of higher order bits, allowing successive computation of priority-encoded address bits, without necessitating the use of clocks or delay elements.

Claims22

Dependent claims

A priority encoder for coupling to a plurality of request lines, said request lines each having an active state and an inactive state and having a relative priority, said priority encoder for detecting an active state of at least one of said request lines and providing an address of a highest priority active request line, said priority encoder comprising:

a plurality of input lines for receiving signals corresponding to the state of said request lines, said plurality of input lines including a first subset of input lines, said first subset of input lines including a first input line;
a plurality of output lines for providing the address of the highest priority active request line, said plurality of output lines including a higher order bit line and a lower order bit line;
an upper logic circuit for driving said higher order bit line, said upper logic circuit having an input coupled to said first input line and an output coupled to said higher order bit line;
a lower logic circuit for driving said lower order bit line, said lower logic circuit having an output coupled to said lower order bit line;
and
a feedback switch circuit coupled between said first input line and said lower logic circuit for selectively coupling said first input line to an input of said lower logic circuit responsive to a feedback signal provided by said upper logic circuit;
wherein said feedback switch circuit couples said first input line to said lower logic circuit input when at least one of the request lines is active and when said first subset of input lines corresponds to a highest priority activated subset as determined by said upper logic circuit, and wherein said feedback switch circuit isolates said first input line from said lower logic circuit input when said first subset of input lines does not correspond to said highest priority activated subset;
whereby said first input line only participates in the determination of said lower order bit upon being within said highest priority activated subset.

5 more elements

A priority encoder for receiving 2.sup.N request signals from 2.sup.N input request lines having sequential addresses and for providing an N-bit output code word equal to the address of the active request signal having the lowest address, comprising:

N output lines for providing said N-bit output code word;
N/2 bus groups, each bus group comprising 4 members for driving two adjacent output lines, each of said 4 members representing a possible state of said two adjacent output lines and being active for indicating said state, said N/2 bus groups being arranged from a highest order bus group for driving the highest two bits of said N-bit output code word to a lowest order bus group for driving the lowest two bits of said N-bit output code word;
N/2 converter circuits for driving said two adjacent output lines associated with each of said N/2 bus groups responsive to the state of said bus group for providing 2 bits of said N-bit output code word;
N/2 logic circuits, each respectively associated with a one of said N/2 bus groups, for driving said bus group, said N/2 logic circuits being arranged from a highest order logic circuit associated with said highest order bus group to a lowest order logic circuit associated with a lowest order bus group;
and
means for combinatorially providing an enable signal to each lower order logic circuit with signals provided by each higher order bus group, wherein said priority encoder is configured to sequentially produce said lowest address in order from said highest order bits to said lowest order bits without the use of delay elements.

3 more elements

Dependencies are inferred from the claim text.