Mechanism for data strobe pre-driving during master changeover on a parallel bus

In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:

• providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock, the first and second strobe signals clocking data in the first and second data transfers, respectively;
• pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer;
• and
• pre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.