High-speed binary adder
AssigneeInternational Business Machines Corporation
InventorsHung Cai Ngo, Sang Hoo Dhong, Joel Abraham Silberman
Life of this patent
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Abstract
A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
Claims18
A binary adder for adding a first multiple-bit addend to a second multiple-bit addend, said binary adder comprising:
- a plurality of rows of carry-lookahead circuits, wherein a first row of said plurality of rows includes a plurality of four-bit group generate circuits and a plurality of four-bit group propagate circuits, wherein each of said four-bit group generate circuits logically combines bits from four different bit positions within said multiple-bit addends to generate a group generate signal, wherein each of said four-bit group propagate circuits logically combines bits from four different bit positions within said multiple-bit addends to generate a group propagate signal;
- a half-sum module for generating a half-sum signal;
- and
- a sum/carry module coupled to said half-sum module and to said plurality of rows of carry-lookahead circuits, wherein said sum/carry module generates a sum signal and a carry signal utilizing said half-sum signal, said generate signals, and said propagate signals.
A processing device, comprising:
- a processing unit;
- a memory associated with said processing unit;
- and
- a binary adder for adding a first multiple-bit addend to a second multiple-bit addend, said binary adder includes:
- a plurality of rows of carry-lookahead circuits, wherein a first row of said plurality of rows includes a plurality of four-bit group generate circuits and a plurality of four-bit group propagate circuits, wherein each of said four-bit group generate circuits logically combines bits from four different bit positions within said multiple-bit addends to generate a group generate signal, wherein each of said four-bit group propagate circuits logically combines bits from four different bit positions within said multiple-bit addends to generate a group propagate signal;
- a half-sum module for generating a half-sum signal;
- and
- a sum/carry module coupled between said half-sum module and said plurality of rows of carry-lookahead circuits, wherein said sum/carry module generates a sum signal and a carry signal by utilizing said half-sum signal, said generate signals, and said propagate signals.
Dependencies are inferred from the claim text.