Division circuits based on power-sum circuit for finite field GF(2.sup.m)
AssigneeNational Science Council
InventorShyue-Win Wei
Life of this patent
Estimating the term…
Abstract
Circuits, designed on the basis of power-sum circuits and inversion (B.sup.-1) computation structure where B is an arbitrary elements of GF(2.sup.m), for performing division computations in finite field GF(2.sup.m), are presented. The circuit can be deemed an extension of the circuit performing inversion (B.sup.-1) computations. With pipeline architecture and on the basis of power-sum circuits, the circuit is featured by simplicity, regularity, and broader application (applicable to arbitrary elements of the finite field) GF(2.sup.m).
Claims12
A division circuit for performing K/H (dividing K by H) computations in a finite field GF(2.sup.m), where H and K are arbitrary elements of GF(2.sup.m), m is the field size of said fnite field GF(2.sup.m), said division circuit comprising:
- a group of m-1 power-sum circuits PK i, where i ranges from 0 to m-2 (i=0, 1, 2, . . . , m-2), each having a first input pin, a second input pin, and an output pin for providing an output signal Sp=A*B.sup.2 in response to the inputting of said A and said B respectively to said first input pin and said second input pin thereof, where * being a multiplication operation over said finite field and both said A and said B being arbitrary elements of said finite field, said second input pin of said PK i where i=m-2 inputting said H, and said first input pin of said PKi where i ranges from 1 to m-2 also inputting said H, said output pin of said PK i providing said second input pin of said Pk.sub.i-1 with said output signal Sp for i ranging from 1 to m-2 (i=1, 2, . . . , m-2), and said first input pin of said PK i for i=0 inputting said K, said K/H is obtained from said output pin of said PK i where i=0.
A division circuit for performing K/H (dividing K by H) computations in a finite field GF(2.sup.m), where H and K are arbitrary elements of GF(2.sup.m), m is the field size of said finite field GF(2.sup.m), said division circuit comprising:
- a multiplex circuit inputting said H and said K for providing a sequence of output signal Ou.sub.i (Ou.sub.1, . . . , Ou.sub.m) where Ou.sub.i =said H for i ranging from 1 to m-1 and Ou.sub.m said K;
- and
- a power-sum circuit PK having a first input pin thereof receiving said sequence of output signal Ou.sub.i, a second input pin thereof receiving an arbitrary element E of said finite field applied thereto, and an output pin thereof providing an output signal Sp=said Ou.sub.i *(said E).sup.2 where * being a multiplication operation over said finite field, said second input pin of said PK inputting the element of 1 of said finite field when said power-sum circuit PK receives said Ou.sub.i where i=1, and said output signal Sp being received by said second input pin of said PK when said power-sum circuit PK receives said Ou.sub.i where i ranges from 2 to m, said output signal Sp provided by said output pin of said power-sum circuit when said power-sum circuit PK receives said Ou.sub.i where i=m, is said K/H.
Dependencies are inferred from the claim text.