Manipulation of boolean values and conditional operation in a microprocessor
AssigneeTexas Instruments Incorporated
InventorsNat Seshan, Laurence Ray Simar, Jr.
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AssigneeTexas Instruments Incorporated
InventorsNat Seshan, Laurence Ray Simar, Jr.
Estimating the term…
A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
A microprocessor, comprising:
A method for performing a plurality of operations in a microprocessor, said microprocessor including an arithmetic logic unit and a plurality of general purpose registers and performing one or more operations in each of a series of clock cycles, said operations comprising one or more arithmetic operations and comprising one or more comparison operations, at least one of said arithmetic operations being conditioned on the result of a comparison operation previously performed, comprising the steps of:
Dependencies are inferred from the claim text.