System and method for uncached store buffering in a microprocessor

A method for efficiently providing blocks of uncached store data to a multiplexed system interface address/data bus comprising the steps of:

• (1) storing a first gatherable uncached store address, said first gatherable uncached store address comprising block-aligned uncached store addresses which access single- or double-word uncached store data;
• (2) storing a second gatherable uncached store address, said second gatherable uncached store address comprising uncached store addresses which access single- or double-word uncached store data;
• (3) comparing said first and second gatherable uncached store addresses;
• (4) selecting an identical gathering mode when said first and second gatherable uncached store addresses are identical;
• (5) selecting a sequential gathering mode when said first and second gatherable uncached store addresses are sequential;
• (6) storing gatherable uncached store data in packed fashion based on said identical and sequential gathering modes;
• and
• (7) issuing said uncached store data to the multiplexed system interface address/data bus.

A computer system, comprising:

• a processor, connected to a memory that stores data;
• a cache, connected to said processor via a microprocessor system interface, for storing a subset of said data;
• an uncached store buffer, connected to said processor, that allows data to be written via a multiplexed system address/data bus from said processor to an external device, while bypassing said cache, said uncached store buffer including:
• detector means, coupled to receive uncached store addresses, for detecting on-the-fly successive uncached store addresses which are identical, and for detecting on-the-fly successive uncached store addresses which are sequential;
• an address buffer, coupled to receive and store a plurality of said uncached store addresses;
• control logic, coupled to an output of said detector means, having a control signal output;
• a data buffer, coupled to receive uncached store data, configured to store a plurality of blocks of said uncached store data in packed fashion, said uncached store data arranged under the control of said control signal output in said data buffer without gaps;
• and
• an output multiplexer, having a first input coupled to an output of said address buffer, a second input coupled to an output of said data buffer, and an output of said output multiplexer coupled to the multiplexed system interface address/data bus, configured to selectively issue said uncached store addresses and said uncached store data to the multiplexed system interface address/data bus.