US 5,963,979 A · System for updating inactive system memory using dual port memory

Abstract

A system for updating an inactive system memory includes a first package set in an active state and having a first processor and a second package set in an inactive state and having a second processor. The first package includes a first buffer memory, a first write control unit for outputting a write control signal and an address signal to the first buffer memory in accordance with a write control signal output from the first processor to the first memory, and a first holding unit for holding update data and an address signal output from the first processor to the first memory, and outputting held contents as data of the first buffer memory in accordance with a write control signal output from the first write control unit to the first buffer memory. The second package has the same arrangement as the first package. The second processor in an inactive state updates the second memory in accordance with update data and address data set for the first memory and stored in the first buffer memory.

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Drawings

Claims11

Dependent claims

A system for updating an inactive memory, comprising:

a first package including:
a first processor having means for generating and outputting a sequence of first address signals, a sequence of first update data corresponding to said sequence of first address signals, a first read control signal, and a first write control signal;
a first memory for read/write of first update data from said sequence of first update data in accordance with first address/signals from said sequence of first address signals, said first read control signal and said first write control signal;
a first dual port buffer memory having an input port for receiving a first data sequence, for storing the received first data sequence in accordance with the first address signal, and having an output port for outputting the stored received first data sequence in response to an access request;
first write control means for generating and outputting a second write control signal and a second address signal in accordance with said first write control signal;
and
first holding means for holding said sequence of first update data and said sequence of first address signals, and for outputting the held sequences as said first data sequence to said first dual port buffer memory, in accordance with said second write control signal;
and
a second package including:
a second processor having means for generating and outputting a sequence of third address signals, a second read control signal, a sequence of second update data corresponding to said sequence of third address signals, and a third write control signal;
a second memory for read/write of second update data from said sequence of second update data in accordance with third address signals from said sequence of third address signals, said second read control signal and said third write control signal;
a second dual port buffer memory for receiving and storing a second data sequence;
second write control means for generating and outputting a fourth write control signal and a fourth address signal in accordance with said the third write control signal;
and
second holding means for holding said sequence of second update data and said sequence of third address signals output from said second processor to said second memory, and for outputting the held sequences as said second data sequence to said second dual port buffer memory, in accordance with said fourth write control signal,
wherein said second processor has means for accessing said first dual port buffer memory by transmitting said access request to the first dual port buffer memory, and has means for updating said second memory to correspond to the sequence of first update data and corresponding sequence of first address data received from said first dual port buffer memory in response to said access request.

13 more elements

A system for updating an inactive system memory, comprising two packages set in a complementary manner in active and inactive states, each of said packages comprising:

a processor memory in which data is stored;
a processor for reading/writing data into/from said processor memory by outputting a sequence of first address signals, a sequence of update data corresponding to said sequence of first address signals, and first read/write control signals;
write control means for outputting a second address signal and a second write control when the first write control signal is output from said processor;
holding means for holding said sequence of update data and the sequence of first address signals output from said processor to said processor memory and for outputting a data sequence comprising the held sequence of update data and sequence of first address signals in accordance with the second write control signal output from said write control means;
and
a dual port buffer memory for storing the data sequence comprising the sequence of update data and the sequence of first address signals output from said holding means in accordance with the second address signal and second write control signal,
wherein the processor of a first one of said packages set in an active state updates the processor memory of said active package by writing the sequence of update data into the processor memory in accordance the corresponding sequence of first address signals and read/write control signals, and
wherein the processor of a second one of said packages set in an inactive state has means for updating the processor memory of said inactive package in accordance with the data sequence comprising the sequence of update data and the sequence of first address signals stored in said buffer memory of said active package, by reading the data sequence out of said dual port buffer memory of said active package.

5 more elements

Dependencies are inferred from the claim text.

Description2,995 words

Summary946 words

#The present invention relates to a system for updating an inactive system memory in a duplex processing apparatus having duplexed packages, each incorporating a microprocessors.

#A duplex processing apparatus is known in which, to improve the reliability of a system to which the apparatus is applied, two packages, each incorporating a microprocessor and having a data processing function, are duplexed. Such a duplex processing apparatus has two identical packages. With this arrangement, even if one package is stopped because of a failure or the like, the other package takes over the processing. Therefore, the overall function is not easily corrupted and a highly reliable apparatus can be realized. In an apparatus having packages duplexed, the contents of a memory of an active system package must be identical to those of a memory of an inactive system package.

#FIG. 3 shows the arrangement of an information processing apparatus in which packages are duplexed in this manner. Referring to FIG. 3, reference numeral 21 denotes a CPU (Central Processing Unit), of a package A, which is a microprocessor; 22, a CPU of a package B, which is a microprocessor; 23, a memory connected to the CPU 21; 24, a memory connected to the CPU 22; 25, a buffer of the package A, which is connected between the CPU 21 and the package B; 26, a buffer of the package B, which is connected between the CPU 22 and the package A; 27, a selection circuit of the package A, which serves to select the CPU 21 or the buffer 26; and 28, a selection circuit of the package B, which serves to select the CPU 22 or the buffer 25.

Brief description of the drawings3 figures

#FIG. 1 is a block diagram showing the arrangement of a system for updating an inactive system memory in a duplex processing apparatus according to an embodiment of the present invention;

#FIGS. 2A to 2F are timing charts showing a write operation with respect to a dual-port memory in FIG. 1; and

#FIG. 3 is a block diagram showing the arrangement of a conventional duplex processing apparatus.

Detailed description1,982 words

#An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the arrangement of a system for updating an inactive system memory according to the present invention.

#Referring to FIG. 1, reference numeral 1 denotes a CPU of a package A, which is a processor; 2, a CPU of a package B, which is a processor; 3, a memory of the package A, which is connected to the CPU 1; 4, a memory of the package B, which is connected to the CPU 2; 5, a counter circuit, of the package A, which is connected to the CPU 1 via a write control bus 104; 6, a counter circuit of the package B, which is connected to the CPU 2 via a write control bus 204; 7, a holding circuit of the package A, which is connected to the CPU 1 via an address bus 102 and a data bus 101; 8, a holding circuit of the package B, which is connected to the CPU 2 via a data bus 201 and an address bus 202; 9, a buffer of the package A, which is connected to the CPU 1 via an address bus 102, read control bus 103 and the data bus 101; 10, a buffer of the package B, which is connected to the CPU 2 via an address bus 202 and a read control bus 203; 11, a dual-port memory (first buffer memory) of the package A in which output data 108 from the holding circuit 7 is written in accordance with an address signal (count value) 106 and a write control signal 107 from the counter circuit 5; 12, a dual-port memory (second buffer memory) of the package B in which output data 208 from the holding circuit 8 is written in accordance with an address signal (count value) 206 and a write control signal 207 from the counter circuit 6; 13, a monitor circuit of the package A, which is connected to the CPU 1 via a data bus 101, an address bus 102, and a write control bus 104; and 14, a monitor circuit of the package B, which is connected to the CPU 2 via a data bus 201, an address bus 202, and a write control bus 204.

#The counter circuits 5 and 6 respectively have control circuits 5a and 6a for outputting latch signals 105 to the holding circuits 7 and 8, and also outputting the write control signals 107 to the holding circuits 7 and 8 and the dual port memories 11 and 12. In addition, the counter circuits 5 and 6 output the address signals 106 and 206 respectively, each consisting of a counter value corresponding to the write control signals 107 and 207, to the dual port memories 11 and 12, respectively.

Facts

Application

08/851,958Filed 6 May 1997 · continuation

Priority

JP 5-07931528 Mar 1994

Granted

5 Oct 1999

Term ended

22 Mar 2015

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification4 codes

G06F 11/1658
Error detection or correction of the data by redundancy in hardware: data re-synchronization of a redundant component, or initial sync of…
G06F 11/2097
Using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements: maintaining the standby controller/processing…
G06F 11/2038
Where processing functionality is redundant: with a single idle spare processing component
G06F
Computing and data processing

System for updating inactive system memory using dual port memory

Life of this patent

System for updating inactive system memory using dual port memory

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims11

Description2,995 words

Drawings

Classification4 codes

Life of this patent

Description2,995 words