Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data

In a computer system comprising:

• a group of central processor units;
• a private cache module included with each central processor unit in the group, each private cache module communicating bilaterally with its central processor unit to receive requests for instruction and operand information blocks and for servicing such requests;
• a CPU bus coupled to all the private cache modules in the group for bilateral communication therewith of address and control signals and information blocks;
• a shared cache unit coupled to the CPU bus for bilateral communication therewith of address and control signals and information blocks;
• each private cache module including a cache memory and a cache controller, the cache controller comprising:
• a processor directory for storing identification words for corresponding information blocks resident in the cache memory, each identification word including a status field indicating a current authority of the one central processor unit with which the private cache module is included to modify the corresponding information block and the validity thereof, a first value in the status field indicating that the one central processing unit has a valid copy of, but does not have authority to modify, the corresponding information block, and a second value in the status field indicating that the one central processing unit has a valid copy of, and does have authority to modify, the corresponding information block;
• a method of servicing requests of the one central processing unit to obtain write permission on a given block of information stored in the cache memory and having an identification word with the status field set to the first value, the method including the steps of:
• A) changing, in the processor directory, the status field of the identification word for the given block of information to the second value;
• B) placing the identification word for the given block of information into a command/address output buffer;
• C) placing an invalidate command into the command/address output buffer to specify, in conjunction with the identification word, a write permission request on the given block of information;
• D) copying all requests placed onto the CPU bus to obtain write permission on blocks of information from all central processor units in the group into a command/address input buffer;
• E) comparing the requests for write permission in the command/address output buffer with the requests for write permission present in the command/address input buffer;
• F) responding to a determination that a request for write permission in the command/address output buffer and a request for write permission in the command/address input buffer identify the same block of information by aborting the request for the same block of information in the command/address output buffer;
• and
• G) responding to a determination that no request for write permission in the command/address output buffer identifies the same block of information as any request for write permission in the command/address input buffer by selectively sending each request to obtain write permission on a block of information out from the command/address output buffer onto the CPU bus.