Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions

#The present invention relates to semiconductor processing. More specifically, the invention relates to a method and apparatus for forming dielectric films over high aspect ratio features at temperatures greater than about 500.degree. C., with the dielectric films having low moisture content and low shrinkage. Embodiments of the present invention are particularly useful to deposit doped dielectric films, such as borophosphosilicate glass (BPSG) films, borosilicate glass (BSG) films, or phosphosilicate glass (PSG) films, and to form ultra-shallow doped regions used, for example, as source/drain junctions or as channel stop diffusions in shallow trench isolation. In addition, embodiments of the present invention may also be used to deposit doped dielectric films used as premetal dielectric (PMD) layers, intermetal dielectric (IMD) layers, or other dielectric layers. Further embodiments of the present invention may further be used to deposit undoped dielectric films, such as undoped silicate glass (USG) films used as shallow trench isolation filling oxides, insulating layers, capping layers, or other layers.

#One of the primary steps in fabricating modem semiconductor devices is forming a dielectric layer on a semiconductor substrate. As is well known, such a dielectric layer can be deposited by chemical vapor deposition (CVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions (homogeneous or heterogeneous) take place to produce a desired film. In a conventional plasma process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film. In general, reaction rates in thermal and plasma processes may be controlled by controlling one or more of the following: temperature, pressure, and reactant gas flow rate.

#Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two-year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing 0.5 .mu.m and even 0.35 .mu.m feature size devices, and tomorrow's plants soon will be producing devices having even smaller feature sizes. As device feature sizes become smaller and integration density increases, issues not previously considered crucial by the industry are becoming of greater concern. In particular, devices with increasingly high integration density have features with high (for example, greater than about 3:1 or 4:1) aspect ratios. (Aspect ratio is defined as the height-to-spacing ratio of two adjacent steps.)

#FIG. 1A is a vertical, cross-sectional view of a CVD apparatus according to the present invention;

#FIG. 1B is a simplified diagram of the system monitor and CVD apparatus 10 in a multichamber system;

#FIG. 1C illustrates a general overview of CVD apparatus 10 in relation to a gas supply panel 80 located in a clean room;

#A. Overview of CVD Reactor

#Embodiments of the present invention are systems, methods and apparatus used for depositing dielectric films at temperatures greater than about 500.degree. C. In particular, such systems, methods and apparatus may be used to deposit undoped dielectric films and doped dielectric films. Such films may be used to form ultra-shallow doped regions, premetal dielectric layers, intermetal dielectric layers, capping layers, oxide filling layers, or other layers. FIG. 1A is a vertical, cross-sectional view of one embodiment of a CVD apparatus 10 according to a specific embodiment. In addition to being capable of depositing dielectric layers, the apparatus according to the present invention has high temperature heating capabilities useful for performing reflow of deposited dielectric layers for planarization, or for driving in dopants from a deposited doped dielectric layer when forming ultra-shallow doped regions. Further, the apparatus can provide efficient cleaning of various CVD chamber components and cleaning of wafer surfaces. CVD apparatus 10 provides these multiple capabilities in situ in a single vacuum chamber 15. Accordingly, multiple process steps may be performed in a single chamber without having the wafer transferred out of that chamber into other external chambers. This results in a lower moisture content on the wafers by eliminating opportunities to absorb moisture from the ambient air and, advantageously increases the dopant retention in the deposited dielectric layer. In addition, performing multiple process steps in a single chamber saves time, which increases the overall throughput of the process.

#Referring to FIG. 1A, CVD apparatus 10 includes an enclosure assembly 200 housing a vacuum chamber 15 with a gas reaction area 16. A gas distribution plate 20 is provided above the gas reaction area 16 for dispersing reactive gases through perforated holes in plate 20 to a wafer (not shown) that rests on a vertically movable heater 25 (also referred to as a wafer support pedestal or susceptor). CVD apparatus 10 further includes a heater/lift assembly 30 for heating the wafer supported on heater 25. Heater/lift assembly 30 also can be controllably moved between a lower loading/off-loading position and an upper processing position indicated by dotted line 13 which is closely adjacent to plate 20, as shown in FIG. 1A. A center board (not shown) includes sensors for providing information on the position of the wafer. As discussed in detail below, heater 25 includes resistively-heated components enclosed in a ceramic, preferably aluminum nitride. In an exemplary embodiment, all surfaces of heater 25 exposed to vacuum chamber 15 are made of a ceramic material, such as aluminum oxide (Al.sub.2 O.sub.3 or alumina) or aluminum nitride. When heater 25 and the wafer are in processing position 13, they are surrounded by a chamber liner 35 along the inside walls 17 of apparatus 10 and by an annular pumping channel 40, formed by chamber liner 35 and a top portion of chamber 15. As discussed in detail below, the surface of chamber liner 35 preferably comprises a ceramic material, such as alumina or aluminum nitride, which serves to lower the temperature gradient between resistively-heated heater 25 (high temperature) and chamber walls 17, which are at a much lower temperature relative to heater 25.