Method of making an interconnect structure employing equivalent resistance paths to improve electromigration resistance
AssigneeUnited Microelectronics Corp.
InventorKuan-Yu Fu
Life of this patent
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AssigneeUnited Microelectronics Corp.
InventorKuan-Yu Fu
Estimating the term…
A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.
A method of forming an interconnect structure in a semiconductor device having improved electromigration resistance, comprising:
A method of forming an interconnect structure in a semiconductor device having improved electromigration resistance, comprising:
Dependencies are inferred from the claim text.
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Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
Characterised by their conductive parts: vias, e.g. via plugs
Semiconductor device manufacturing: process: electromigration resistant metallization
Semiconductor device manufacturing: process: making metal-insulator-metal device
Term ended 17 Aug 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The invention relates to an interconnect structure in an integrated circuit, and more particularly to a method of improving electromigration (EM) resistance by modifying the interconnect structure.
2. Description of the Related Art
FIG. 1 shows a conventional structure of conductive lines with a 1.times.4 vertical contact/via array;
FIG. 2 shows an equivalent circuit of the contact/via array shown in FIG. 1;
FIG. 3 shows a conventional structure of conductive lines with a 4.times.4 vertical contact/via array;
In a preferred embodiment according to the invention, an interconnect structure with two conductive lines is provided. A load resistor is added between each contact/via and each conductive line, so that the equivalent resistance including the load resistor and the two conductive lines thereof is identical to achieve the uniformity of the current flow. Therefore, the EM lifetime of each contact/via is enhanced. A detailed description of the invention is presented in the following paragraphs with accompanying drawings FIG. 4, FIG. 5, FIG. 6 and FIG. 7.
Referring to FIG. 4, FIG. 6 and FIG. 7, conductive lines M1, M2 are formed over a substrate 600 in which the conductive line M1 is isolated from the conductive line M2 by a dielectric layer 602 on the substrate 600. A 4.times.4 contact/via array comprising 16 contacts/vias A.sub.11, . . . , A.sub.44 is formed on the substrate 600 to electrically connect the conductive line M1 and the conductive line M2. According to practical requirement, a load resistor is added to each row and each column of the contacts/vias. As shown in FIG. 4 these load resistors are formed by first forming slots with various length within the conductive line M2 and the conductive line M1 for each corresponding column and row of contacts/vias. For the contact/via rows A.sub.1i to A.sub.4i, slots R.sub.2i to R.sub.4i are respectively inserted within the conductive line M1 between each of the contact/via rows A.sub.1i to A.sub.4i. For the contact/via column A.sub.i1 to A.sub.i4, slots R.sub.i2 to R.sub.i4 are respectively inserted within the conductive line M2 between each of the contact/via column A.sub.i1 to A.sub.i4. These slots, R.sub.2i to R.sub.4i and R.sub.i2 to R.sub.i4, filled with dielectric material are themselves parallel and respectively extend in the direction that the conductive lines M1, M2 extend. The resistance of the load resistors depends on the current path from conductive line M1 to conductive line M2 through contact/via array. The longer the current path is, the smaller the load resistor is, that is, the shorter the length l.sub.4 of the slot is.
Assuming that each contact/via A.sub.11, A.sub.12, . . . , A.sub.44 has a resistance of r.sub.c, and the conductive layer M1 between each contact/via A.sub.11, A.sub.12, . . . , A.sub.44 has a resistance of r, according to the equivalent circuit shown in FIG. 5, taking the first row as an example, a zero resistance is added to the first contact/via element A.sub.11 with the highest equivalent resistance due to the longest current path from conductive line M1 to conductive line M2 through A.sub.11. With the second contact/via element A.sub.12 having a second highest equivalent resistance, a load resistor with resistance r is serially connected. A load resistor having resistance 3r is serially connected with the third contact/via element A.sub.13, and a load resistor having resistance 6r is serially connected with the fourth contact/via element A.sub.14. Since the slots R.sub.i2 to R.sub.i4 are disposed within the conductive line M2 between each contact/via columns A.sub.11, . . . , A.sub.14 to occupy a part of the section area, the current from the contact/via A.sub.11, . . . , A.sub.4 passes through different section areas when the current flows through the conductive line M2. Thus, a current path from the conductive line M1 to the conductive line M2 through each of the contact/via A.sub.11, . . . , A.sub.14 and the load resistor corresponding to the contact/via has an identical equivalent resistance. When a total current of 4I is input into the conductive line M1, each contact/via A.sub.11 to A.sub.14 receives a current of I.