Combined trench isolation and inlaid process for integrated circuit formation

A method of forming a semiconductor structure, the method comprising the steps of:

• providing a semiconductor substrate having an upper surface and an active region of the upper surface;
• forming a trench region in the semiconductor substrate, wherein the trench region extends below the upper surface of the semiconductor substrate;
• forming a dielectric region over a portion of the semiconductor substrate to fill the trench region and overly the active region of the semiconductor substrate;
• and
• forming a gate opening in the dielectric region over a portion of the active region to define a transistor gate electrode location.

A method for forming a semiconductor structure, the method comprising the steps of:

• providing a semiconductor substrate;
• forming a dielectric region having a recessed region;
• forming an opening in the dielectric region;
• forming a conductive region over the dielectric region;
• polishing, with a first polishing environment, the conductive region to form a conductive plug within the opening and a conductive defect in the recessed region;
• changing the first polishing environment to a second polishing environment to remove an upper portion of the dielectric region adjacent to the conductive defect to further expose the conductive defect;
• and
• changing the second polishing environment to a third polishing environment to remove substantially all of the conductive defect.

A method of forming a semiconductor structure, the method comprising the steps of:

• providing a semiconductor substrate;
• forming an oxide layer over the semiconductor substrate;
• forming a first conductive layer over the oxide layer;
• forming a first opening into the semiconductor through the oxide layer and the first conductive layer;
• forming a dielectric to fill the first opening and overlie the first conductive layer;
• forming a second opening in the dielectric layer over an active area of the semiconductor substrate to expose a portion of the first conductive layer;
• forming a spacer within the second opening;
• forming a second conductive layer to fill remaining portions of the second opening;
• polishing the second conductive layer to remove substantially all of the second conductive layer positioned outside the second opening;
• removing a portion of the dielectric layer positioned outside the first opening to form a dielectric fill region in the first opening whereby trench isolation is formed;
• and
• removing a portion of the first conductive layer that is exposed by the step of removing a portion of the dielectric layer.