Method of fabricating a MOS device with a localized punchthrough stopper
AssigneePowerchip Semiconductor Corp.
InventorHorng-Nan Chern
Life of this patent
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Abstract
A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy layer is preferably made of silicon nitride, which has a high etching selectivity with respect to the oxide material forming sidewall spacers of MOS devices. The localized punchthrough stopper is formed at the boundary of the lightly-doped regions and the channel by implanting impurities through the well resulting from the removal of a portion of the dummy layer adjacent to the gate structure.
Claims20
A method of fabricating a MOS device with a localized punchthrough stopper on a substrate, comprising:
- forming a composite structure including a gate oxide layer and a conductive polysilicon layer on the substrate;
- depositing a first dielectric layer on the top and the sides of the composite structure and the exposed substrate;
- depositing a second dielectric layer on the first dielectric layer;
- etching back the second dielectric layer to expose the first dielectric layer over the composite structure;
- isotropically etching the first dielectric layer to remove a portion of the first dielectric layer on the top and the sides of the composite structure, thereby defining at least one well on at least one side of the composite structure;
- doping the exposed substrate adjacent to the composite structure through said at least one well to form a punchthrough stopper;
- refilling said at least one well on the sides of the composite structure with a third dielectric layer;
- anisotropically etching the second dielectric layer and the third dielectric layer to form sidewall spacers;
- removing exposed portions of the first dielectric layer;
- and
- forming doped regions in the exposed substrate.
A method of forming a punchthrough stopper in the structure of a MOS device on a substrate, comprising the steps of:
- forming a composite structure including a gate oxide layer and a conductive polysilicon layer on the substrate;
- covering the composite structure with a first dielectric layer;
- depositing a second dielectric layer on the first dielectric layer, wherein a portion of the second dielectric layer over the composite structure is thinner than a portion of the second layer directly over the substrate;
- removing the portion of the second dielectric layer over the composite structure using the first dielectric layer as an etching stop layer;
- isotropically etching the first dielectric layer to remove a portion of the first dielectric layer on the top and the sides of the composite structure, thereby defining at least one well on at least one side of the composite structure;
- and
- doping the exposed substrate adjacent to the composite structure through said at least one well to form a punchthrough stopper.
A method of fabricating a MOS device with a localized punchthrough stopper on a substrate, comprising:
- forming a composite structure including a gate oxide layer and a polysilicon layer on the substrate;
- depositing a first dielectric layer on the top and the sides of the composite structure and the exposed substrate;
- depositing a second dielectric layer on the first dielectric layer;
- removing a portion of the second dielectric layer;
- isotropically etching the first dielectric layer to remove a portion of the first dielectric layer on the top and the sides of the composite structure, thereby defining at least one well on at least one side of the composite structure;
- doping the exposed substrate adjacent to the composite structure through said at least one well to form a punchthrough stopper.
Dependencies are inferred from the claim text.