Asymmetrical MOSFET with gate pattern after source/drain formation

A process for forming a transistor, comprising:

• providing a semiconductor substrate;
• forming a first masking layer on said semiconductor substrate, wherein said first masking layer masks portions of an upper surface;
• implanting a first impurity distribution into said semiconductor substrate prior to forming a conductive gate structure, wherein first masking layer masks said implant whereby said first impurity distribution is aligned to said first masking layer within said semiconductor substrate;
• removing said first masking layer from said semiconductor substrate;
• forming a gate dielectric layer on an upper surface of said semiconductor substrate;
• forming a conductive gate structure on an upper surface of said gate dielectric layer wherein a first sidewall of said conductive gate structure is laterally aligned above a first boundary of said first impurity distribution and wherein a second sidewall of said conductive gate structure is laterally displaced from a second boundary of said first impurity distribution;
• and
• implanting a second impurity distribution into said semiconductor substrate, wherein said conductive gate structure masks said implanting whereby said second impurity distribution is aligned to said conductive gate structure such that said second impurity distribution is laterally displaced with respect to said first impurity distribution on a first side of said transistor and further wherein said second impurity distribution is substantially aligned with said first impurity distribution on a first side of said transistor.

A semiconductor process for forming first and second transistors, comprising:

• providing a semiconductor substrate, wherein said semiconductor substrate includes a first channel region laterally disposed between a first source region and a first LDD region, and further wherein said first LDD region is laterally disposed between said first channel region and a first drain region, and further wherein said semiconductor substrate includes a second channel region isolated from said first channel region by an isolation structure intermediate between said first and second channel regions, and further wherein said second channel region is laterally disposed between a pair of second lightly doped regions wherein said pair of lightly doped regions are displaced between a second pair of source/drain regions;
• introducing a first impurity distribution selectively into said first source region, said first drain region, and a second pair of second source/drain regions of said semiconductor substrate prior to forming first and second conductive gate structures;
• forming a gate dielectric layer on an upper surface of said semiconductor substrate;
• forming first and second conductive gate structures on an upper surface of said gate dielectric layer wherein a first sidewall of said first conductive gate structure is laterally aligned above a boundary between said first source region and said first channel region and further wherein a second sidewall of said first conductive gate structure is laterally aligned above a boundary between said first channel region and said first LDD region and further wherein sidewalls of said second conductive gate structure are aligned above boundaries between said second channel regions and said second pair of lightly doped regions, whereby said second sidewall of said first conductive gate structure is laterally displaced from said first drain region by a lateral dimension of said first LDD region;
• implanting a second impurity distribution into said semiconductor substrate, wherein said first and second conductive gate structures serve as an implant mask during whereby said second impurity distribution is aligned to said first and second conductive gates respectively, and further wherein a peak concentration of said first impurity distribution is greater than a peak concentration of said second impurity concentration whereby the presence of said second impurity distribution within said first source region and said drain region of said semiconductor substrate does not significantly alter the electrical characteristics of said source or drain regions;
• forming sidewall spacer structures on said first and second conductive gate structures;
• and
• wherein said first transistor comprises said first conductive gate structure, said first source region, said first LDD region, and said first drain region whereby said first transistor includes a lightly doped drain proximal to said first drain region to reduce a maximum electric field within said first channel region, and further wherein said first transistor lacks a lightly doped region proximately to said first source region thereby reducing a parasitic resistance of said source region, and further wherein said second transistor includes said second conductive gate structure and said pair of second source/drain regions and wherein said second transistor lightly doped regions proximal to its pair of source/drain region for bidirectional operation of said second transistor.