Method of forming retrograde well structures and punch-through barriers using low energy implants

#The invention relates to semiconductor fabrication. More specifically, the invention relates to the fabrication of retrograde well structures in CMOS devices.

#Complementary Metal Oxide Semiconductor (CMOS) technology involves the pairing of complementary n-channel and p-channel MOS transistors to form low power integrated circuits. Each pair of complementary transistors is formed in close proximity on a substrate, with the p-channel transistor being formed in a heavily n-doped region of the substrate, and the n-channel transistor being formed in a heavily p-doped region. Low power consumption has made CMOS the technology of choice for very large scale integrated circuits, such as microprocessors, dynamic random access memories (DRAMS) and erasable programmable read only memories (EPROMS).

#A major problem with CMOS devices is known as "latch-up." With the p-channel and n-channel transistors being in close proximity, conditions can arise that allow large currents to flow between the drain of one transistor and the source of the complementary transistor. The large currents, in turn, cause high power dissipation, which can stop the CMOS device from functioning or even destroy the CMOS device.

#FIG. 1 is an illustration of a CMOS device having its retrograde well being fabricated;

#FIG. 2 is a illustration of the lattice structure of a silicon substrate and dopant atoms channeling into the substrate, the substrate forming a part of the CMOS device shown in FIG. 1;

#FIG. 3 is a first doping profile for the retrograde well of the CMOS vice shown in FIG. 1;

#FIG. 1 shows a CMOS device 10 under fabrication. The CMOS device 10 includes a substrate 12 having a <100> crystal axis orientation. A p-type substrate 12, for example, could be lightly doped with an impurity such as boron in a concentration between 1.times.10.sup.14 atoms/cm.sup.3 and 5.times.10.sup.15 atoms/cm.sup.3, or the p-type substrate could be a heavily doped p.sup.+ -type substrate upon which a thin, epitaxial layer of lightly doped p-type material is grown.

#Isolation islands 14 are formed on the substrate 12 by conventional techniques. For example, a pad-oxide layer is deposited on the substrate 12 and a layer of nitride is deposited on the oxide layer by chemical vapor deposition. Portions of the nitride layer 14 are etched away to expose the oxide layer at the areas where the islands are to be grown. The substrate 12 is heated to temperatures approaching 1000.degree. C., as the exposed oxide is slowly grown into the isolation islands 14. The substrate 12 is heated until the isolation islands 14 reach a desired thickness. Isolation islands 14 for a 0.35 micron CMOS device , for example, might have thicknesses of 5500 angstroms, and they might be spaced apart by 0.4 microns. After the isolation islands 14 are grown, the nitride and underlying pad-oxide are removed from the substrate 12. Remaining between the isolation islands 14 is a bare substrate.

#An n-well mask 16 is formed on the substrate 12 and patterned to expose the bare surface at the location where an n-well 18 will be formed. A p-type transistor will eventually be formed in the n-well 18. The region 20 where an n-type transistor will be formed remains covered by the mask 16. The n-well mask 16 can be formed from photoresist and patterned by a conventional technique such as photolithography.