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AssigneeGeneral Electric Company
InventorsDale Marius Brown, Richard Joseph Saia, John Adam Edmond, John Williams Palmour
Estimating the term…
A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity .alpha.6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer is epitaxially grown on the substrate layer. A steep-walled groove is etched through the n+ SiC layer and partially into the p SiC layer at a location on the substrate where a MOSFET gate structure is desired. Subsequently, a thin layer of silicon dioxide and a layer of gate metal are successively deposited over the entire structure. The gate metal layer is deposited with sufficient thickness to substantially fill the groove. A layer of photoresist is applied to the entire surface of the gate metal layer. The photoresist and the underlying gate metal are then reactive ion etched down to the oxide layer, leaving gate metal remaining only in the groove. The gate metal and oxide layer form the self-aligned gate structure wherein the walls of the groove are automatically aligned with the edges of drain and source regions that are formed on either side of the groove.
A method of fabricating a metal oxide semiconductor device having a self-aligned gate structure comprising the steps of:
A method of fabricating a metal oxide semiconductor device having a self-aligned gate structure comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Being Group IV materials comprising two or more elements, e.g. SiGe: silicon carbide
Manufacture or treatment: of igbts
Of FETs having insulated gates [IGFET]: of lateral single-gate IGFETs
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
Term ended 7 Aug 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to silicon carbide metal-oxide-semiconductor field effect transistors (MOSFETs) having self-aligned gate electrodes and a method of fabricating these MOSFETs.
2. Description of the Prior Art
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself, however, both as to its organization and method of operation, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 depicts, in cross section, a p-type SiC substrate having an epitaxial layer grown thereon;
FIG. 2 is a top view of the structure shown in FIG. 1, with an annular groove cut through the epitaxial layer into the substrate;
Although the invention is applicable to both n-channel and p-channel MOSFET devices and their manufacture, for purposes of simplicity the following description will consider fabrication only of a MOSFET having an n-channel.
FIG. 1 depicts a SiC substrate 100 having a heavily-doped n type conductivity (designated n+) layer 102 of SiC epitaxially and uniformly deposited thereon. A typical dopant for n+ layer 102 may comprise nitrogen at a concentration of 10.sup.18 -10.sup.20 centimeters.sup.-3. Substrate 100 is of an .alpha.6H monocrystalline structure, lightly doped to p type conductivity with a dopant such as aluminum or boron at a concentration of 10.sup.14 -10.sup.16 centimeters.sup.-3. Although substrate 100 may support multitudes of individual transistors, as well known in the art, for simplicity the description will focus upon creation of one transistor having an annular structure or two transistors having linear structures.
As shown in FIGS. 2, 3 and 4, grooves 104, having sidewall 105 and bottom 107, are etched through epitaxial layer 102 and into substrate 100. Each groove 104 defines a future location for a gate structure for each SiC MOSFET on the substrate. Groove shape may vary from an annular ring, as depicted in FIG. 2, to an arrangement of substantially rectangular slots which is depicted in FIG. 3 as two parallel grooves. The cross-sectional views of FIGS. 2 and 3 are the same, as shown in FIG. 4. However, the annular groove of FIG. 2 is used to generate a single annular transistor structure having drain region 112 circumscribed by the gate structure, while the groove pair shown in FIG. 6 is used to create a pair of transistors having parallel linear gate structures with source region 111 and drain region 112 on either side of each gate groove 104.