Integrated circuit using a back gate voltage for burn-in operations

#This invention relates in general to the field of electronic devices and, more particularly, to an integrated circuit utilizing a back-gate bias voltage during burn-in operations.

#Designers of integrated circuits constantly strive to make the devices smaller so that more active devices can be placed on a single integrated circuit and so that the integrated circuit will have a lower cost. As devices become smaller, it becomes increasingly more difficult to prevent the formation of parasitic devices. One example of a parasitic device is the formation of a parasitic bipolar transistor between the source and drain of a field effect transistor with the bulk substrate being the remaining terminal of the bipolar transistor. In CMOS architectures, adjoining field effect devices can both create parasitic bipolar transistors in such a manner that a parasitic silicon controlled rectifier is formed. This condition is referred to as latch up and can destroy the normal operation of the CMOS system.

#After an integrated circuit has been completed, the system is often tested using a burn-in process. During thus burn-in process, a higher than normal voltage is applied to the terminals which act as supply voltages within the: circuit. The circuit is then exercised at the higher than normal operating voltage. If the device is susceptible to failure, the burn-in process can cause such failures to occur to isolate and eliminate the susceptible devices. For example, burn-in is a useful way of eliminating devices that have defective gate oxides formed within field effect: transistors. Because of the higher voltages used during burn-in, an integrated circuit is ordinarily much more susceptible to both formation of unwanted parasitic devices and in some cases, latch up of the device.

#A more complete understanding of the present invention and the advantage thereof may be acquired by referring to the accompanying figures in which like reference numbers indicate like features and wherein:

#FIG. 1 is a greatly enlarged cross-sectional, elevational schematic diagram of a field effect transistor that may comprise a portion of an integrated circuit constructed according to teachings of the present invention;

#FIG. 2 is a graphical depiction of the transfer characteristics of the transistor shown in FIG. 1;

#FIG. 1 is a cross-sectional diagram which illustrates a portion of an integrated circuit formed on a semiconductor substrate 10. A p-well 12 is formed in an outer surface of the semiconductor substrate 10. P-well 12 contains an n-channel field effect transistor indicated generally at 14. Transistor 14 comprises a gate conductor 16 separated from the outer surface of the semiconductor substrate 10 by a gate insulator layer 18. On opposite sides of gate conductor 16 are formed a source region 20 and a drain region 22. Source and drain regions 20 and 22 comprise regions of p-well 12 that have been doped with n-type impurities. In contrast, a substrate contact region 24 is formed proximate transistor 14 within p-well 12. Contact region 24 comprises a region of p-well 12 that has been doped with additional p-type impurities. Contact 24 can be used to electrically contact p-well 12 and the bulk of substrate 10.

#In the exemplary circuit shown in FIG. 1, substrate 10 comprises a p-type substrate. For example, substrate 10 may comprise a substrate construction using epitaxial methods that has a resistivity on the order of 0.01 to 0.03 .OMEGA..multidot.cm. Alternatively, substrate 10 may comprise a non-epitaxial substrate that has a resistivity on the order of 10 to 15 .OMEGA..multidot.cm. As will be discussed more completely herein, the resistivity of the substrate is an important consideration in how the back-gate bias voltage of the present invention is applied. If the resistivity is low enough as in the example of an epitaxially-created substrate, few contacts to the substrate such as contact 24 are necessary. If on the other hand, the resistivity of the substrate is higher, as in the case of a non-epitaxial substrate, more contacts to the substrate such as contact region 24 are necessary in order to maintain the consistent and evenly dispersed back-gate bias voltage necessary to prevent the latch up condition.

#FIG. 1 also schematically illustrates the presence of a parasitic npn bipolar transistor 26 and a parasitic resistor 28. The emitter of parasitic transistor 26 corresponds to the source region 20 of transistor 14. Similarly, the collector of transistor 26 corresponds to the drain region 22 of transistor 14. The base of transistor 26 corresponds to the substrate 10 and the p-well 12. The inherent resistance of the p-well 12 provides the resistance between the base of transistor 26 and the substrate contact 24.