APAP I/O programmable router

A parallel array computer system, comprising:

• a plurality of nodes interconnected by a plurality of inter-node communication links in an inter-node array topology, each node having a plurality of processor memory elements, each processor memory element of each node including:
• a processor and a local memory coupled to said processor;
• an internal input and output port coupled to a parallel internal communication path directly connected to another processor memory element in the same node for bidirectional inter-processor communication therebetween;
• an external input and output port coupled to a parallel external communication path directly connected to a processor memory element of another node for bidirectional inter-processor communication therebetween, wherein the parallel external communication path is one of said plurality of inter-node communication links;
• and
• wherein the local memory includes stored instructions selectively executed by the processor for controlling routing data and control information with another processor memory element of the same node along said parallel internal communication path, and between the node containing the processing memory element and said another node along said parallel external communication path, independent of a centralized router providing routing for each of the processor memory elements within the same node, thereby providing for a router that is fully distributed among each of the processing memory elements of each of the nodes of the parallel array computer system;
• and
• wherein said inter-node array links are exclusively provided by each parallel external communication path of said nodes, and said inter-node array topology is not dependent on said parallel internal communication path of each of said plurality of nodes.