Software reconfigurable target I/O in a circuit emulation system

The target I/O system for coupling an emulator having a plurality of data bits to a target system, comprising:

• a plurality of PSI modules coupled to the emulator, each PSI module sending input bits to the emulator and receiving output bits and output enable bits from the emulator in a predetermined order;
• a cable coupled to each of the PSI modules;
• and
• a plurality of PUI modules, each of the PUI modules connected to a respective one of the PSI modules through a respective cable, and further coupled to the target system to transmit the input, output and output enable bits to and from the target system in the predetermined order, wherein the output bits and the input bits are sent to and from the emulator, respectively, during different time slices.

The target I/O system for coupling an emulator having a plurality of data bits to a target system, comprising:

• a plurality of PSI modules coupled to the emulator, each PSI module sending input bits to the emulator and receiving output bits and output enable bits from the emulator in a predetermined order;
• a cable coupled to each of the PSI modules;
• and
• a plurality of PUI modules, each of the PUI modules connected to a respective one of the PSI modules through a respective cable, and further coupled to the target system to transmit the input, output enable bits to and from the target system in the predetermined order, wherein there are twelve PSIs and twelve PUIs.

The target I/O system for coupling an emulator having a plurality of data bits to a target system, comprising:

• a plurality of PSI modules coupled to the emulator, each PSI module sending input bits to the emulator and receiving output bits and output enable bits from the emulator in a predetermined order;
• a cable coupled to each of the PSI modules;
• and
• a plurality of PUI modules, each of the PUI modules connected to a respective one of the PSI modules through a respective cable, and further coupled to the target system to transmit the input, output and output enable bits to and from the target system in the predetermined order, wherein there are eleven PSIs and eleven PUIs.

A target I/O system for coupling an emulator having a plurality of data bits to a target system, comprising:

• a plurality of PSI modules coupled to the emulator, each PSI module sending input bits to the emulator and receiving output bits and output enable bits from the emulator in a predetermined order;
• a cable coupled to each of the PSI modules;
• and
• a plurality of PUI modules, each of the PUI modules connected to a respective one of the PSI modules through a respective cable, and further coupled to the target system to transmit the input, output and output enable bits to and from the target system in the predetermined order, wherein the input, output and enable bits are sent during four time slices .