US 5,963,730 AGranted

Method for automating top-down design processing for the design of LSI functions and LSI mask layouts

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsMasahiko Toyonaga, Michiaki Muraoka, Hirokazu Iida

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Abstract

A netlist between functional macros is entered. Based on the netlist, an outline layout process for a functional macro is performed and physical specifications for the functional macro are determined from an outline layout produced by the outline layout process. Thereafter, a logic synthesis process is performed on the basis of the physical specifications determined. Based on the outline layout, a logic, obtained by the logic synthesis, is laid out. This makes it possible to reduce the number of times a circuit synthesis process is redone, taking into account a laying-out at an upper-stage functional design process in which no gate level is specified. For this reason, an improved LSI automatic design method is provided which is able to complete an LSI layout design, in which the LSI area and the LSI delay value are optimized, in a short period of time.

Claims10

Dependent claims

An LSI (large-scale Integrated circuit) automatic design method for the automatic design of an LSI by means of design automation on the basis of the arithmetic/storage functioning of an electronic computer, said LSI automatic design method comprising;

(a) a netlist input process of inputting a netlist between functional macros;
(b) a macro outline layout process of creating an outline layout for functional macros by which relative positions of said functional macros are determined on the basis of said netlist and for determining a physical specification including areas and delays of said functional macros from said outline layout;
(c) a logic synthesis process of performing synthesis processing under said physical specification including areas and delays of said functional macros,
wherein said logic synthesis process is performed after said macro outline layout process is performed;
and
(d) a layout process of putting logic circuits obtained in said logic synthesis process in said relative positions of said functional macros which are determined by said outline layout and laying out said logic circuits.

3 more elements

Dependencies are inferred from the claim text.