Method for automated electromigration verification

A computer-implemented method for detecting electromigration violations in an integrated circuit design, the integrated circuit design having a functional hierarchy including a plurality of top-most level functional blocks each containing a plurality of functional cells, a plurality of external networks each interconnecting two or more of the top-most level functional blocks and together with the interconnected top-most level functional blocks forming a plurality of top-level nets, and further including a plurality of internal networks each contained within a respective one of the top-most level functional blocks and each interconnecting two or more functional cells within the respective one top-most level functional block, each of the external and internal networks including conductive signal traces and each of the functional cells having a drive strength associated therewith, said method comprising:

• providing electromigration process rules for conductive signal traces of the integrated circuit design;
• obtaining parasitic resistance and parasitic capacitance values for each conductive signal trace of the integrated circuit design;
• propagating upward within the functional hierarchy the parasitic resistance and capacitance values of the conductive signal traces of the integrated circuit design;
• determining a lumped resistance, a lumped capacitance and a lumped drive strength of each of the top-most level functional blocks;
• determining a lumped resistance and lumped capacitance for each external network;
• calculating at least one current value for each top-level net from the lumped resistance, the lumped capacitance and the lumped drive strength of the external networks and the top-most level functional blocks interconnected thereby;
• determining minimum electromigration dimensions for the conductive signal traces of the integrated circuit design based on the at least one current value and said electromigration process rules for each of the top-level nets;
• determining design dimensions of the conductive signal traces of the integrated circuit design;
• comparing the design dimensions with the minimum electromigration dimensions;
• and
• identifying violations of the fabrication process rules for the conductive signal traces of the integrated circuit when the design dimensions are less than the minimum electromigration dimensions.