Method to partition clock sinks into nets
AssigneeInternational Business Machines Corporation
InventorsDavid James Hathaway, Roger Sherman Rutter
Life of this patent
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Abstract
A method of designing the clocking circuitry of an integrated circuit chip. The load sinks are assigned to clock nets, each clock net having less then a maximum load. The first step is selecting a pair of clock nets for improvement. Next, a subset of the load sinks of the pair of clock nets are assigned to each clock net. Thereafter, the unassigned load sinks are assigned in all possible combinations to each of the pair of clock nets. A penalty function for each load sink assignment, and the assignment having the best penalty function is kept.
Claims18
A method of designing the clocking circuitry of an integrated circuit chip having a plurality of separate clock nets and a plurality of sinks, comprising the steps of:
- making an initial assignment of a sink to one of two or more separate clock nets of said integrated circuit chip;
- selecting two of said clock nets including all sinks assigned to either of said two clock nets;
- removing said all assigned sinks from said two selected clock nets, and re-assigning each of less than said all sinks, to one or the other of said two selected clock nets;
- thereafter, forming all possible combinations of re-assigning each of the remaining sinks of said all sinks, to one or the other of said two selected clock nets;
- computing the value of a penalty function for each of said all possible combinations of assignment;
- and
- keeping that said combination of assignment having the best computed value of said penalty function.
A computer program product containing executable code for execution by a computer for designing the clocking circuitry of an integrated circuit chip having a plurality of separate clock nets and a plurality of sinks, said computer program product comprising:
- means for making an initial assignment of each sink to one of two or more separate clock nets;
- means for selecting two of said clock nets including all sinks assigned to either of said two clock nets;
- means for removing said all assigned sinks from said two selected clock nets, and re-assigning each of less than said all sinks, to one or the other of said two selected clock nets;
- means for thereafter forming all possible combinations of re-assigning each of the remaining sinks of said all sinks, to one or the other of said two selected clock nets;
- means for computing the value of a penalty function for each said combination of assignment;
- and
- means for keeping that said combination of assignment having the best computed value of said penalty function.
A computer system for designing the clocking circuitry of an integrated circuit chip having a plurality of separate clock nets and a plurality of sinks, comprising:
- means for making an initial assignment of each sink to one of two or more separate clock nets;
- means for selecting two of said clock nets including all sinks assigned to either of said two clock nets;
- means for removing said all assigned sinks from said two selected clock nets, and re-assigning each of less than said all sinks, to one or the other of said two selected clock nets;
- means for thereafter forming all possible combinations of re-assigning each of the remaining sinks of said all sinks, to one or the other of said two selected clock nets;
- means for computing the value of a penalty function for each said combination of assignment;
- and
- means for keeping that said combination of assignment having the best computed value of said penalty function.
Dependencies are inferred from the claim text.