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US 5,963,723 AGranted
System for pairing dependent instructions having non-contiguous addresses during dispatch
AssigneeInternational Business Machines Corporation
InventorHung Qui Le
Life of this patent
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Abstract
In a superscalar data processing system, instructions, which are dependent upon each other, are paired for dispatch to a plurality of execution units. Pairing results in instructions being paired that may not necessarily be located at contiguous addresses. Pairing may be performed by comparing general purpose register source pointers and general purpose register target pointers of the various instructions. Pairing may also be accomplished by comparing target identification numbers of source operands with target identification numbers of target instructions.
Claims41
A method for dispatching instructions in a data processing system, the method comprising the steps of:
- determining if a first instruction is dependent upon a second instruction;
- and
- pairing the first and second instructions for dispatch, wherein the first and second instructions do not have contiguous addresses.
A processor comprising:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- circuitry for determining if an operand of a first instruction depends upon a result of a second instruction, wherein the first and second instructions are included in a group of instructions transferred from the instruction queue to the pre-execution queue, wherein the first and second instructions do not have contiguous addresses;
- circuitry for pairing the first and second instructions for dispatch to the execution cluster when a general purpose register source pointer of the first instruction matches a general purpose register target pointer of the second instruction.
2 more elements
A data processing system, comprising:
- a processor coupled to an input device, an output device, and a memory device by a bus system, where in the processor further comprises:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- means for determining if an operand of a first instruction depends upon a result of a second instruction;
- and
- means for pairing the first and second instructions for dispatch to the execution cluster, wherein the first and second instructions do not have contiguous addresses.
4 more elements
A method for dispatching instructions in a data processing system, the method comprising the steps of:
- determining if a first instruction is dependent upon a second instruction;
- and
- pairing the first and second instructions for dispatch, wherein the first and second instructions may or may not have contiguous addresses, wherein the first instruction is being transferred from an instruction queue to a pre-execution queue and the second instruction is already located in the pre-execution queue, wherein the determining step further comprises the step of comparing a general purpose register source pointer of the first instruction with a general purpose register target pointer of the second instruction;
- and
- if there is the match between the source pointer and the target pointer, then as the first instruction is in-gated into the pre-execution queue the first instruction is linked to the second instruction.
2 more elements
A method for dispatching instructions in a data processing system, the method comprising the steps of:
- determining if a first instruction is dependent upon a second instruction;
- and
- pairing the first and second instructions for dispatch, wherein the first and second instructions may or may not have contiguous addresses,
- wherein the determining step further comprises the steps of:
- determining if an operand of the first instruction depends upon the result of the second instruction;
- comparing a general purpose register source pointer of the first instruction residing within an instruction queue with a general purpose register target pointer of the second instruction residing within the instruction queue;
- and
- comparing the general purpose register source pointer of the first instruction residing within the instruction queue with a general purpose register target pointer of a third instruction residing within a pre-execution queue,
- wherein the comparing steps are performed in parallel.
6 more elements
A data processing system, comprising:
- a processor coupled to an input device, an output device, and a memory device by a bus system, wherein the processor further comprises:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- means for determining if an operand of a first instruction depends upon a result of a second instruction;
- and
- means for pairing the first and second instructions for dispatch to the execution cluster, wherein the first and second instructions may or may not have contiguous addresses,
- wherein the determining means further comprises:
- means for comparing a general purpose register source pointer of the first instruction residing within an instruction queue with a general purpose register target pointer of the second instruction residing within the instruction queue;
- and
- means for comparing the general purpose register source pointer of the first instruction residing within the instruction queue with a general purpose register target pointer of a third instruction residing within a pre-execution queue,
- wherein the two comparing means are operated in parallel.
9 more elements
A method for dispatching instructions in a data processing system, the method comprising the steps of:
- determining if a first instruction is dependent upon a second instruction;
- and
- pairing the first and second instructions for dispatch, wherein the first and second instructions do not have contiguous addresses, wherein the first and second instructions are included in a group of instructions transferred from an instruction queue to a pre-execution queue,
- wherein the determining step further comprises the step of comparing a general purpose register source pointer of the first instruction with a general purpose register target pointer of the second instruction, wherein when the comparing step results in more than one possible pairing of first and second instructions, the youngest second instruction is paired with the oldest first instruction.
1 more element
A method for dispatching instructions in a data processing system, the method comprising the steps of:
- determining if a first instruction is dependent upon a second instruction;
- and
- pairing the first and second instructions for dispatch, wherein the first and second instructions do not have contiguous addresses, wherein the first instruction is being transferred from an instruction queue to a pre-execution queue and the second instruction is already located in the pre-execution queue,
- wherein the determining step further comprises the step of comparing a general purpose register source pointer of the first instruction with a general purpose register target pointer of the second instruction, and wherein when the comparing step results in more than one possible pairing of first and second instructions, the youngest second instruction is paired with the oldest first instruction.
1 more element
A processor comprising;
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- circuitry for determining if an operand of a first instruction depends upon a result of a second instruction, wherein the first and second instructions are included in a group of instructions transferred from the instruction queue to the pre-execution queue;
- and
- circuitry for pairing the first and second instructions for dispatch to the execution cluster when a general purpose register source pointer of the first instruction matches a general purpose register target pointer of the second instruction, wherein when the first and second instructions do not have contiguous addresses, and wherein when the comparing step results in more than one possible pairing of first and second instructions, the youngest second instruction is paired with the oldest first instruction.
3 more elements
A processor comprising:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- circuitry for determining if an operand of a first instruction depends upon a result of a second instruction, wherein the first and second instructions are included in a group of instructions transferred from the instruction queue to the pre-execution queue;
- circuitry for pairing the first and second instructions for dispatch to the execution cluster when a general purpose register source pointer of the first instruction matches a general purpose register target pointer of the second instruction;
- circuitry for determining if an operand of the first instruction depends upon a result of a third instruction, wherein the third instruction is already located in the pre-execution queue;
- and
- circuitry for pairing the first instruction with the third instruction for dispatch to the execution cluster when the general purpose source pointer of the first instruction matches a general purpose register target pointer of the third instruction,
- wherein when the first and third instructions do not have contiguous addresses, and wherein when the comparing step results in more than one possible pairing of first and third instructions, the youngest third instruction is paired with the oldest first instruction.
6 more elements
A data processing system, comprising:
- a processor coupled to an input device, an output device, and a memory device by a bus system, wherein the processor further comprises:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- means for determining if an operand of a first instruction depends upon a result of a second instruction;
- and
- means for pairing the first and second instructions for dispatch to the execution cluster, wherein the first and second instructions may or may not have contiguous addresses,
- wherein the first and second instructions are included in a group of instructions transferred from the instruction queue to the pre-execution queue,
- wherein the determining means further comprises means for comparing a general purpose register source pointer of the first instruction with a general purpose register target pointer of the second instruction,
- wherein when the first and second instructions do not have contiguous addresses, and wherein when the comparing step results in more than one possible pairing of first and second instructions, the youngest second instruction is paired with the oldest first instruction.
7 more elements
A data processing system, comprising:
- a processor coupled to an input device, an output device, and a memory device by a bus system, wherein the processor further comprises:
- an instruction queue;
- a pre-execution queue coupled to the instruction queue;
- an execution cluster coupled to the pre-execution queue;
- means for determining if an operand of a first instruction depends upon a result of a second instruction;
- and
- means for pairing the first and second instructions for dispatch to the execution cluster, wherein the first and second instructions may or may not have contiguous addresses,
- wherein the first instruction is being transferred from the instruction queue to the pre-execution queue and the second instruction is already located in the pre-execution queue,
- wherein the determining means further comprises:
- means for comparing a general purpose register source pointer of the first instruction with a general purpose register target pointer of the second instruction,
- wherein when the first and second instructions do not have contiguous addresses, and wherein when the comparing step results in more than one possible pairing of first and second instructions, the youngest second instruction is paired with the oldest first instruction.
8 more elements
Dependencies are inferred from the claim text.