Microprocessor system with capability for asynchronous bus transactions

Abstract

A microprocessor-based data processing system (2) in which asynchronous bus transactions are performed is disclosed. The disclosed embodiments include one or more microprocessors (5) of the x86-architecture type, compatible with the P54C bus protocol, preferably Pentium-compatible microprocessors, as the central processing units (CPUs) of the system. A CPU (5.sub.r) requests an asynchronous bus transaction, in a first disclosed embodiment, by presenting a combination of control signals that is unused in conventional x86-architecture systems; the controller chipset (27) determines whether the transaction may be performed in an asynchronous manner, and later returns an acknowledge or non-acknowledge code to the requesting CPU (5.sub.r). The microprocessors (5) include certain pins, in this first embodiment, corresponding to conventional Pentium-compatible output pins but which now have receiver circuitry for receiving the acknowledge and non-acknowledge codes, along with the transaction identifier. If the transaction is accepted as asynchronous, the identifier is used to later identify the transaction when access is granted. A second disclosed embodiment provides an immediate indication of the acceptability of the requested transaction as of the asynchronous type, so that unacceptable transactions may be immediately processed in synchronous fashion. A third disclosed embodiment uses an additional terminal to indicate the acknowledge or non-acknowledge response.

Dependencies are inferred from the claim text.