Two-pin distributed ethernet bus architecture

A two-pin bus interface for coupling a network module to a two-conductor intermodule bus, the bus interface comprising a state machine having:

• an idle state in which idle codes are transmitted onto the intermodule bus;
• an arbitration state in which module identifying codes are transmitted onto the intermodule bus by a state machine in a master mode, to arbitrate for bus access;
• a send state in which data codes are transmitted onto the intermodule bus and transmitted to local ports associated with the bus interface;
• multiple master collision states in which collision codes are transmitted onto the intermodule bus, the master collision states including a master receive collision state for announcing a receive collision detected on one local port associated with the bus interface, and a master transmit collision state for announcing a transmit collision involving activity on more than one local port, at least one of which is associated with this bus interface;
• an arbitration wait state in which a state machine in a slave mode participates in arbitration with at least one other state machine;
• a receive state in which a state machine in the slave mode receives data from the bus and transmits it to local ports associated with the bus interface;
• multiple slave collision states in which collision codes are received from the bus and relayed to the local ports associated with the bus interface, the slave collision states including a slave receive collision state for processing an announcement of a receive collision detected by another bus interface, and a slave transmit collision state for processing an announcement of a transmit collision detected by another bus interface;
• a set of state machine commands defining conditions necessary to effect transitions from state to state;
• and
• a set of state machine responses defining functions performed by the state machine when making a transition from one state to another;
• wherein state machines of multiple bus interfaces connected to the bus operate in cooperation to perform distributed arbitration for bus access and to transfer data and state information from one bus interface to another;
• and wherein
• the intermodule bus has first and second lines, which carry signals of "0" state or "1" state,
• the idle codes are "0" state signals on both first and second lines,
• data and state information is transmitted in a signal sequence beginning with identifying codes during arbitration and followed by a data sequence or collision state announcement,
• the module identifying codes transmitted during arbitration include successive identifying bits transmitted onto the first line and "1" codes simultaneously transmitted onto the second line,
• the data codes are transmitted as pairs of complementary data bits on the first and second lines, and
• the collision codes begin with a "1" code on both first and second lines, and continue with a string of "1's" on the first line and a string of either "1's" or "0's" on the second line, to differentiate between receive collisions and transmit collisions.