Method and apparatus for correcting error in control field in cache memory
AssigneeNEC Corporation
InventorMidori Muramatsu
Life of this patent
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Abstract
A control field in a store-in cache memory in a multi-processor system includes a valid bit, an exclusive bit, and a clean bit. An error in the control field is not only detectable but also correctable by a control field correction circuit. The control field correction circuit includes a mode register holding inhibit correction flags, inhibit correction-in-part flags, and detect inconsistency flags.
Claims29
An error correction circuit for a cache memory having a control field, said error correction circuit comprising:
- a first correcting circuit for correcting at least one bit of a plurality of bits in the control field in a fixed, predetermined manner;
- and
- a second correcting circuit for correcting said at least one bit based on a status of said cache memory.
A cache memory comprising:
- a tag memory for holding an address tag and a control field;
- an error detection circuit for detecting error in said control field;
- and
- an error correction circuit for correcting, based on a status of said cache memory, the error detected by said error detection circuit.
A method of correcting error in a cache memory having a control field, said method comprising steps of:
- detecting an error in said control field of said cache memory;
- and
- correcting said error by correcting at least one bit of a plurality of bits in the control field based on bits other than said at least one bit and a status of said cache memory.
Dependencies are inferred from the claim text.