Pipelined pyramid processor for image processing systems
AssigneeSarnoff Corporation
InventorsGooitzen Sieman van der Wal, Michael Wade Hansen
Life of this patent
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Abstract
A pipelined parallel processor (PPP) integrated onto a single integrated circuit. The PPP includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits may be, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch which routes data between the frame store controller, the filtering unit, function circuits, external input channels, and external output channels.
Claims9
An image processing apparatus comprising:
- a single memory;
- an integrated circuit connected to the single memory, the integrated circuit including
- processing means for processing a plurality of image signals,
- means for filtering at least one of the plurality of image signals, and
- a five port frame store controller having
- means for concurrently storing at least two image signals in the memory, and
- means for concurrently reading at least two image signals from the memory, and
- a crosspoint switch for concurrently routing at least two image signals to the filtering means, the storing means, the reading means, and the processing means.
An image processing apparatus comprising:
- a single memory;
- an integrated circuit connected to the single memory, the integrated circuit including
- processing means for processing a plurality of image signals,
- means for filtering at least one of the plurality of image signals,
- a five port frame store controller having
- (a) means for concurrently storing at least two image signals in the memory, and
- (b) means for concurrently reading at least two image signals from the memory;
- a crosspoint switch for concurrently routing at least two image signals to the filtering means, the storing means, the reading means, and the processing means.
An image stabilization apparatus comprising:
- a single memory;
- an integrated circuit connected to the single memory, the integrated circuit including:
- means for receiving an image signal including a first frame and a second frame;
- means for generating further image signals including a first Laplacian pyramid signal from the first frame and a second Laplacian pyramid signal from the second frame;
- a five port frame store controller having
- means for concurrently storing at least two of said image signal and said further image signals in the memory;
- and
- means for concurrently reading at least two of said image signal and said further image signals from the memory;
- and
- a crosspoint switch for concurrently routing at least two of said image signals to the filter means, the storing means, the reading means and the processing means;
- means for producing alignment values between the first Laplacian pyramid signal and the second Laplacian pyramid signal;
- and
- means for warping one of the first and second frames using the alignment values.
Dependencies are inferred from the claim text.