US 5,963,609 AGranted

Apparatus and method for serial data communication between plurality of chips in a chip set

AssigneeUnited Microelectronics Corp.

InventorCheng-Wang Huang

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Abstract

An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Claims16

Dependent claims

An apparatus for serial data communication between a first IC chip and a second IC chip, comprising:

(a) a transfer request signal generator, located on at least one of the first IC chip and the second IC chip, for generating a transfer request signal;
(b) a control signal generator, located on the first IC chip, responsive to the transfer request signal, for generating a transfer control signal;
(c) a clock signal generator, responsive to the transfer request signal, for generating a synchronization clock signal, wherein the synchronization clock signal has a plurality of cycle periods;
(d) a counter, located on the first IC chip and the second IC chip, for counting the plurality of cycle periods of the synchronization clock signal to produce a cycle count;
(e) a data transmitter, located on at least one of the first IC chip and the second IC chip, responsive to the transfer control signal, for transmitting data under control of the cycle count;
and
(f) a data receiver, located on at least the other of the at least one of the first IC chip and the second IC chip, responsive to the transfer control signal, for receiving the data transmitted by the data transmitter under control of the cycle count.

4 more elements

Dependencies are inferred from the claim text.