US 5,963,608 A · Clock extractor for high speed, variable data rate communication system

Abstract

To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.

Claims8

Dependent claims

An apparatus for extracting, from a digital data signal, an embedded clock signal that falls within a data clock signal range comprising:

a data rate estimator that is coupled to receive said digital data signal and is operative to derive therefrom a data rate estimate signal representative of an estimate of the data rate of data contained in said digital data signal;
a phase-locked loop that includes a reference clock signal generator, a phase detector having a first input coupled to receive said digital data signal, a second input coupled to receive a signal representative of said reference clock signal, and an output, and a controllably sweepable loop filter coupled in a loop path including said reference clock signal generator and said phase detector;
and
a controller which is operative to controllably inhibit a sweep of said loop filter, while varying said reference clock signal generated by said reference clock signal generator, until said reference clock signal reaches a value established in accordance with said data rate estimate signal, and to thereafter controllably sweep said loop filter, and thereby said phase-locked loop, until said phase detector produces an output representative that said phase-locked loop is locked to said embedded clock signal of said digital data signal.

1 more element

Dependencies are inferred from the claim text.

Clock extractor for high speed, variable data rate communication system

Life of this patent

Clock extractor for high speed, variable data rate communication system

Life of this patent

Abstract

Claims8