Phase error cancellation method and apparatus for high performance data recovery
AssigneeSun Microsystems, Inc.
InventorsRobert J. Drost, Robert J. Bosnyak
Life of this patent
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Abstract
A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
Claims18
An apparatus to recover data bits from a data stream with reduced phase error, comprising:
- a data delay pipe coupled to receive the data stream, and configured to delay the data bits by a first amount;
- a phase lock mechanism coupled to the data delay pipe, and configured to control the data delay pipe to delay the data bits by the first amount;
- a clock generator configured to generate a clock signal;
- a clock delay pipe coupled to the clock generator, and configured to delay the clock signal by a second amount;
- and
- a data stream sampling element coupled to receive the delayed data bits and the delayed clock signal, and configured to sample the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
A method for recovering data bits of a data stream with reduced phase error, comprising the steps of:
- receiving the data stream;
- generating a clock signal;
- delaying the data bits by a first amount;
- generating a data delay control signal for controlling the data bits delaying step to delay the data bits by the first amount;
- delaying the clock signal by a second amount;
- and
- sampling the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
A receiver to recover data bits from a received data stream, comprising:
- a clock generator configured to generate a clock signal;
- a phase lock mechanism configured to perform lower bandwidth tracking to align a phase of the data bits to a phase of the clock signal;
- a data delay pipe configured to delay the data bits by a first amount in response to the lower bandwidth tracking by the phase lock mechanism;
- a phase error correction mechanism configured to perform higher bandwidth tracking to compensate for a remaining difference in phase between the data bits and the clock signal after the lower bandwidth tracking by the phase lock mechanism;
- and
- a data sampling element configured to capture the data bits using the clock signal after the higher bandwidth tracking by the phase error correction mechanism.
A method to recover data bits from a data stream, comprising the steps of:
- receiving the data bits of the data stream;
- generating a clock signal;
- performing lower bandwidth tracking to align a phase of the data bits to a phase of the clock signal;
- delaying the data bits by a first amount in response to the lower bandwidth tracking performing step:
- performing higher bandwidth tracking to compensate for a remaining difference in phase between the data bits and the clock signal after performing the lower bandwidth tracking;
- and
- capturing the data bits using the clock signal after performing the higher bandwidth tracking.
Dependencies are inferred from the claim text.