Communication signal receiver with sampling frequency control

A communication signal receiver, comprising:

• a sampling circuit that samples an analog data signal and that converts the analog data signal to a digital replica of the analog data signal responsive to transitions of a sampling clock signal;
• adjustment determination circuitry that analyzes at least a portion of the digital samples and determines an adjustment to the timing of the sampling in response to the analysis, the adjustment determination circuitry generating an adjustment signal indicative of the determined adjustment;
• clock generation circuitry that generates the sampling clock signal, the clock generation circuitry including circuitry that modifies the frequency of the sampling clock signal responsive to the adjustment signal, the sampling clock signal including:
• a) first circuitry that receives a first clock signal having transitions which alternate, from a first logic state to a second logic state and back to the first logic state;
• and
• b) second circuitry that produces a modulated clock signal by removing x transitions from each of consecutive sets of L transitions of the first clock signal, where x and L are integers and 0<x<L.
• c) circuitry that divides the modulated clock signal by M to generate the sampling clock signal, where M is an integer evenly divisible into L-x with no remainder, such that the sampling clock signal has exactly one transition for any set of M transitions of the modulated clock signal.