Synchronism detection and demodulating circuit

A synchronism detection and demodulating circuit for performing synchronism detection and demodulation of a reproduced data stream which was recorded based on a modulating scheme whereby a digital data stream consisting of n-bit words is divided every m words and these are grouped as a unit, each group being added with extra `p` bits (`p` is not an integer multiple of `m`), to produce one block of {(n>m)+p} bits, comprising:

• a first circuit which shapes serially inputted regenerative data into a parallel form using an irregularly frequency-divided clock signal which is frequency divided by m/((n.times.m )+p);
• a second circuit which detects sync patterns from the data in the parallel form from the first circuit whilst deleting a redundant part in the parallel data;
• a third circuit which detects ID information from the data in the parallel form from the first circuit whilst deleting the redundant part in the parallel data;
• a fourth circuit which effects synchronism protection based on the information from the second and third circuits;
• and
• a fifth circuit which rearranges the data in the parallel form from the first circuit, based on the information from the fourth circuit whilst deleting the extra bits and redundant part in the parallel data.