Audio decoder circuit and method of operation

A data processing system, comprising:

• an arithmetic logic unit operable to perform arithmetic and logical operations;
• an instruction memory for storing microcode instructions executable by the system to process a data stream;
• an instruction register connected to the instruction memory for holding a first microcode instruction;
• an execution control state machine coupled to the instruction register and operable to direct the performance of the arithmetic and logical operations in response to the first microcode instruction;
• a multiplexor with a first input connected to the instruction register, a second input connected to the execution control state machine, and an output connected to the arithmetic logic unit;
• wherein the arithmetic logic unit is operable to perform the arithmetic and logical operations in response to a set of instruction bits from the instruction register or from the execution control state machine;
• a data shifter interconnected with the arithmetic logic unit and operable to receive a first data field from the data stream and to provide a selected number of data bits to the arithmetic logic unit by a sharing operation;
• a shift counter with control inputs connected to the execution control state machine, the shift counter is connected to the data shifter and is operable to control the shifting operation of the data shifter;
• and
• a load counter with control signals connected to the execution control state machine, the load counter is connected to the data shifter and is operable to assert a first control signal when the first data field is completely shifted out of the data shifter.

A data processing system, comprising:

• system decoder circuitry with an input for receiving a stream of encoded data and an output for providing a stream of encoded audio data selected from the stream of encoded data;
• first buffer circuitry with an input connected to the system decoder circuitry for receiving the stream of encoded audio data;
• audio decoder circuitry connected to the first buffer and operable to decode the stream of encoded audio data to form a stream of decoded audio data;
• second buffer circuitry connected to the audio decoder circuitry operable to receive the stream of decoded audio data;
• hardware filter circuitry connected to the second buffer operable to filter the stream of decoded audio data;
• and
• wherein the audio decoder circuitry further comprises:
• an arithmetic logic unit operable to perform arithmetic and logical operations;
• an instruction memory for storing microcode instructions executable by the system to process a data stream;
• an instruction register connected to the instruction memory for holding a first microcode instruction;
• and
• an execution control state machine coupled to the instruction register and operable to direct the performance of the arithmetic and logical operations in response to the first microcode instruction.