Application specific integrated circuit chip and method of testing same
AssigneeLSI Logic Corporation
InventorsRochit Rajsuman, Ching-Yen Ho
Life of this patent
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Abstract
An application specific integrated circuit having an embedded microprocessor and core including a memory array, self tests at full operational speed utilizing the computational power of the embedded microprocessor for deterministic testing performed by core specific test algorithms implemented in the assembly code of the embedded microprocessor.
Claims15
A self testing method for an integrated circuit system having microprocessor means and associated core means including a memory array, comprising:
- storing in the memory array computer readable codes indicative of a group of pre-test functional commands executable by the microprocessor means to help facilitate subsequent testing management of all of the functional commands executable by the microprocessor means and the associated core means;
- instructing the microprocessor means to retrieve in seriatim, individual ones of the pre-test functional commands to facilitate the separate testing of each one of the functional commands executable by the microprocessor means and the associated core means during a test mode of operation;
- instructing the microprocessor means to execute in seriatim each individual one of the pre-test functional commands in a manner that the core means produce the same results if the pre-test functional commands perform their intended function;
- comparing said respective core means results to each other
- generating a default signal whenever the core means results are not the same;
- and
- generating a continue testing signal whenever all individual ones of the pre-test functional commands executed by the microprocessor means performed their intended functions correctly.
A self testing integrated circuit system having microprocessor means and associated core means including a memory array, comprising:
- functional test program means responsive during a test mode of operation for causing the microprocessor means to execute in seriatim individual functional commands executable by the integrated circuit system in a manner that the core means produce the same results if the individual functional commands perform their intended function;
- fault detection means coupled to the microprocessor means and the associated core means for generating a default signal whenever the core means results are not the same;
- and
- interface means coupled to the microprocessor means and said fault detection means for permitting computer readable code means indicative of the functional commands executable by the integrated circuit system to be stored in the memory array and for permitting said default signal to be detected for quality assurance purposes during said test mode of operation.
A method of testing an integrated circuit system having at least a microprocessor and associated cores including a memory array, comprising:
- storing in the memory array computer readable codes indicative of functional commands executable by the microprocessor and the associated cores;
- instructing the microprocessor to retrieve in seriatim individual ones of the functional commands executable by the microprocessor and the associated cores;
- instructing the microprocessor to execute in seriatim each individual one of the retrieved functional commands in a manner that the associated cores produce the same results if the functional commands perform their intended function;
- and
- generating a default signal whenever the associated core means results are not the same.
Dependencies are inferred from the claim text.