Apparatus for reproducing digital signal
AssigneePioneer Electronic Corporation
InventorsHideki Kobayashi, Kiyoshi Tateishi
Life of this patent
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Abstract
An apparatus for reproducing a digital signal which converts a signal read from a recording medium on which a digital signal is recorded into a series of sample values with an A/D converter, detects a phase error from the series of sample values, generates a gain phase error signal by providing the phase error with a predetermined gain, corrects the phase of a clock signal based on the gain phase error signal, and uses the clock signal with the phase thereof corrected as a sampling clock.
Claims9
An apparatus for reproducing a digital signal based on a signal read from a recording medium on which the digital signal is recorded, comprising:
- reading means for reading a signal from said recording medium;
- an Analog to Digital converter for sequentially sampling said read signal in response to a sampling clock to convert the sampled signal into a series of sampled values;
- decoding means for decoding said series of sample values to output a reproduced digital signal;
- phase error detection means for detecting a phase error from said series of sample values;
- a recording medium discrimination circuit for detecting characteristics of the recording medium and outputting a recording medium type signal;
- memory means for storing a predetermined gain;
- gain setting means for outputting a gain phase error signal based on said phase error, said predetermined gain, and in part on said recording medium type signal;
- and
- clock generation means for generating a clock signal which has been subjected to phase correction based on said gain phase error signal as said sampling clock.
An apparatus for reproducing a digital signal based on a signal read from a recording medium on which the digital signal is recorded, comprising:
- reading means for reading a signal from said recording medium;
- an Analog to Digital converter for sequentially sampling said read signal in response to a sampling clock to convert the sampled signal into a series of sampled values;
- decoding means for decoding said digital signal based on said series of sample values to output a reproduced digital signal;
- phase error detection means for detecting a phase error from said series of sample values;
- memory means for storing a predetermined gain;
- gain setting means for outputting a gain phase error signal by providing said phase error with said predetermined gain;
- and
- clock generation means for generating a clock signal which has been subjected to phase correction based on said gain phase error signal as said sampling clock
- drop-out detection means for detecting a drop-out;
- and
- input prohibiting means for prohibiting the input of said phase error obtained from said series of sample values at the time of a drop-out to said clock generation means when the drop-out is detected.
An apparatus for reproducing a digital signal based on a signal read from a recording medium on which the digital signal is recorded, comprising:
- a signal reader for reading a signal from said recording medium;
- an Analog to Digital converter for sequentially sampling said read signal in response to a sampling clock to convert the sampled signal into a series of sampled values;
- a decoder for decoding said series of sample values to output a reproduced digital signal;
- a phase error detector for detecting a phase error from said series of sample values;
- a recording medium discrimination circuit for detecting characteristics of the recording medium and outputting a recording medium type signal;
- a memory for storing a predetermined gain;
- a gain setting mechanism for outputting a gain phase error based on said phase error, said predetermined gain, and in part on said recording medium type signal;
- and
- a clock generator for generating a clock signal which has been subjected to phase correction based on said gain phase error signal as said sampling clock.
An apparatus for reproducing a digital signal based on a signal read from a recording medium on which the digital signal is recorded, comprising:
- a signal reader for reading a signal from said recording medium;
- an Analog to Digital converter for sequentially sampling said read signal in response to a sampling clock to convert the sampled signal into a series of sampled values;
- a decoder for decoding said series of sample values to output a reproduced digital signal;
- a phase error detector for detecting a phase error from said series of sample values;
- a recording medium discrimination circuit for detecting characteristics of the recording medium and outputting a recording medium type signal;
- a memory for storing a predetermined gain;
- a gain setting mechanism for outputting a gain phase error based on said phase error, said predetermined gain, and in part on said recording medium type signal;
- and
- a clock generator for generating a clock signal which has been subjected to phase correction based on said gain phase error signal as said sampling clock
- a drop-out detector for detecting a drop-out;
- and
- an input prohibiter for prohibiting the input of said phase error obtained from said series of sample values at the time of a drop-out to said clock generator when the drop-out is detected.
An apparatus for reproducing a digital signal based on a signal read from a recording medium on which the digital signal is recorded, comprising:
- a signal reader for reading a signal from said recording medium;
- an Analog to Digital converter for sequentially sampling said read signal in response to a sampling clock to convert the sampled signal into a series of sampled values;
- a decoder for decoding said series of sample values to output a reproduced digital signal;
- a phase error detector for detecting a phase error from said series of sample values;
- a recording medium discrimination circuit for detecting characteristics of the recording medium and outputting a recording medium type signal;
- a memory for storing a predetermined gain;
- a gain setting mechanism for outputting a gain phase error based on said phase error, said predetermined gain, and in part on said recording medium type signal;
- and
- a clock generator for generating a clock signal which has been subjected to phase correction based on said gain phase error signal as said sampling clock,
- wherein said phase error detector comprises a sample value extraction circuit which determines an extracted sample value and a gradient signal from said series of sample values and a polarity switching circuit that outputs said phase error from said extracted sample value and said gradient signal.
Dependencies are inferred from the claim text.