Sequential access memory with low consumption
AssigneeSGS-Thomson Microelectronics S.A.
InventorsAlain Pomet, Bernard Plessier
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Abstract
A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.
Claims18
A sequential access memory working at the rate of a clock signal and comprising:
- N bistable and synchronous register elements N, each storing an information bit, said register elements being divided into L groups each comprising P register elements that are series-connected and simultaneously activated or not;
- a multiplexer for connecting and the output of the last register element of each group to the output of the memory;
- and
- a management unit for storing N information bits arriving in serial form at the input of the memory, by activating the register elements of a given group at least P times consecutively during a part of the time corresponding to an equal number of consecutive periods of the clock signal and by not activating the register elements of the given group for the rest of the time, so that each group stores P consecutive information bits from among the N bits.
A sequential access memory comprising:
- N bistable and synchronous register elements N, each storing an information bit, said register elements being divided into L groups each comprising P register elements;
- a multiplexer for connecting and the output of the last register element of each group to the output of the memory;
- and
- a management unit for storing N information bits arriving in serial form at the input of the memory, by activating the register elements of a given group at least P times consecutively during a part of the time corresponding to an equal number of consecutive periods of the clock signal and by not activating the register elements of the given group for the rest of the time, so that each group stores P consecutive information bits from among the N bits.
A sequential access memory comprising:
- N bistable and synchronous register elements N, each storing an information bit, said register elements being divided into L groups each comprising P register elements with P being an integer power of two;
- a multiplexer for connecting and the output of the last register element of each group to the output of the memory;
- and
- a management unit for storing N information bits arriving in serial form at the input of the memory, by activating the register elements of a given group at least P times consecutively during a part of the time corresponding to an equal number of consecutive periods of the clock signal and by not activating the register elements of the given group for the rest of the time, so that each group stores P consecutive information bits from among the N bits.
A method for operating a sequential access memory of a type comprising N bistable and synchronous register elements N, each storing an information bit, said register elements being divided into L groups each comprising P register elements, the method comprising the steps of:
- using a multiplexer for connecting and the output of the last register element of each group to the output of the memory;
- and
- storing N information bits arriving in serial form at the input of the memory, by activating the register elements of a given group at least P times consecutively during a part of the time corresponding to an equal number of consecutive periods of the clock signal and by not activating the register elements of the given group for the rest of the time, so that each group stores P consecutive information bits from among the N bits.
Dependencies are inferred from the claim text.