US 5,963,503 AGranted

Synchronous systems having secondary caches

AssigneeSamsung Electronic Co., Ltd.

InventorYoung-Dae Lee

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Abstract

A cache memory uses at least two synchronous memory devices operable of responding to an external clock signal and performing a bank operation mode. The memory device includes a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal, a first decoder generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line which is preliminarily selected, a control signal generating circuit receiving the informing signal and generating a control signal responding to the internal clock signal, and a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected. When the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.

Claims2

Dependent claims

A synchronous memory device operable of responding to an external clock signal comprising:

a memory cell array having a plurality of memory cells arranged in a matrix formed of rows and columns;
a plurality of first and second word lines, a connection ratio of the first and second word lines being 1:n (n is at least greater than 1);
a clock generator for generating an internal clock signal responding to the external clock signal;
a control logic for generating an informing signal denoting a non-selection of the memory device, the informing signal responding to the internal clock signal;
a first decoder for receiving row address signals to designate one of the first word lines, and for generating a first selection signal to designate one of the second word lines and a second selection signal to designate one of the first word lines corresponding to the first word line preliminarily selected;
a control signal generating circuit for receiving the informing signal and for generating a control signal responding to the internal clock signal;
and
a second decoder for receiving the first and second selection signals and for selecting the first word line, when the memory device is being selected;
whereby, when the memory device goes to a selection state from a non-selection state, the control signal is enabled until the first and second selection signals are applied to the second decoder, during a cycle time of the informing signal.

6 more elements

Dependencies are inferred from the claim text.