Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing

A synchronous type semiconductor memory device, comprising:

• a phase synchronization circuit for generating an internal clock signal synchronized in phase with an externally supplied external clock signal, said phase synchronization circuit including a voltage controlled oscillator having a feedback loop from an output portion thereof to an input portion thereof and having an oscillating frequency controlled by a control voltage corresponding to a phase difference between said external clock signal and said internal clock signal;
• a read clock generator for generating a read clock signal from said internal clock signal for external outputting when data is read, said read clock generator including a variable delay circuit having a same structure as said voltage controlled oscillator except for said feedback loop and receiving a signal corresponding to said internal clock signal at an input portion thereof;
• and
• a vernier setting circuit for setting a delay amount of said variable delay circuit in accordance with an external command.