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AssigneeSamsung Electronics, Coi., Ltd.
InventorsSung-geun Lee, Woo-seop Jeong
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A clock signal generating circuit for use in a synchronous dynamic random access memory device. The clock signal generating circuit includes an input buffer for converting an externally supplied system clock signal having a first voltage level into a clock signal having a voltage level necessary for operating with the internal circuitry of the memory device. An enable path circuit generates a second transition of an internal clock signal which occurs substantially simultaneous the second transition of the system clock signal. The enable path circuit generates the first transition of the internal clock signal after the internal clock signal is maintained at the second state for a predetermined interval responsive to first and second disable signals. Finally, a disable path circuit receives the clock signal generated from the input buffer and supplies the first and second disable signals to the enable path circuit.
A clock signal generating circuit for generating an internal clock signal for a synchronous DRAM device, comprising:
A clock signal generating circuit for generating an internal clock signal for a synchronous DRAM device, comprising:
A method for generating an internal clock signal for a synchronous DRAM device, the internal clock signal having a first edge, a second edge, and a predetermined pulse duration for defining an internal clock signal pulse, the first edge occurring substantially simultaneous a first edge of an external system clock signal, the method comprising:
A clock signal generating circuit for generating an internal clock signal for a synchronous DRAM device, comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Term ended 11 Jun 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic clock signal generating circuit for use in a synchronous Dynamic Random Access Memory (DRAM) device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a dynamic clock signal generating circuit for use in a synchronous DRAM device according to the present invention; and
FIG. 2 is an operational timing chart of the signals shown in FIG. 1.
FIG. 1 shows a dynamic clock signal generating circuit for use in a synchronous DRAM device according to the present invention. The clock signal generating circuit generates an internal clock signal PCLK with a minimum delay with respect to the system clock signal CLK. The clock signal generating circuit includes an input buffer 10, an enable path circuit 100, and a disable path circuit 200. The input buffer 10 converts the system clock signal CLK into a clock signal having a voltage level necessary for operating with the internal circuitry. For example, if the system clock signal CLK has a Transistor-Transistor Logic (TTL) voltage level and the internal circuitry operates using Complementary Metal Oxide Semiconductor (CMOS) voltage levels, input buffer 10 converts the system clock signal CLK from a TTL voltage level into a clock signal having a CMOS voltage level.
The enable path circuit 100 consists of PMOS transistors 40, 41, and 45, NMOS transistors 42, 43, and 47, and inverters 44 and 46. The disable path circuit 200 consists of PMOS transistors 21 and 22, an NMOS transistor 23, and inverters 20, 24-27, and 30-31.
In the enable path circuit 100, PMOS transistor 41 and NMOS transistor 42 and PMOS transistor 40 and NMOS transistor 43 each form an inverter. In the disable path circuit 200, PMOS transistor 22 and NMOS transistor 23 also form an inverter. Inverters 30 and 31 form a delay chain. The amount of delay of inverters 30 and 31 determine the pulse width of the internal clock signal PCLK. The inverters 24 and 25 constitute a latch. Each inverter substantially consists of a pair of PMOS and NMOS transistors. To improve operating speed, the gate length of the PMOS transistor within inverter 46 is preferably 180 .mu.m which is longer than the typical NMOS gate length. Moreover, the gate length of an NMOS transistor within the inverter 44 is preferably 50 .mu.m which is longer than the typical gate length of about 10 .mu.m. The gate lengths of PMOS transistors 40 and 41 are preferably about 60 .mu.m and 40 .mu.m, respectively.