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US 5,963,500 AGranted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTadayuki Taura, Shigeru Atsumi, Hironori Banba
Life of this patent
Estimating the term…
Abstract
A decoder circuit selectively controls the transfer gate group. The transfer gate group is stacked so as to form a tree structure having multiple stages of transfer gates and enable a monitoring bus line to be connected to any column in a memory cell array. This configuration enables the current in each memory cell to be monitored at an external pad via a single bus line, which reduces the area occupied by the bus lines, suppressing an increase in the chip size.
Claims19
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells each to be accessed in accordance with selected row and column are arranged in a matrix;
- an external terminal used to monitor the current in each of said plurality of memory cells;
- a single bus line, connected to said external terminal, for conducting said current to said external terminal;
- a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, for selectively connecting said bus line to any column in said memory cell array;
- and
- a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group.
3 more elements
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells each to be accessed in accordance with selected row and column are arranged in a matrix;
- an external terminal used to monitor the current in each of said plurality of memory cells;
- a single bus line, connected to said external terminal, for conducting said current to said external terminal;
- a transfer gate group, provided between said bus line and said memory cell array and stacked so as to form a tree structure having multiple stages of transfer gates, for selectively connecting said bus line to any column in said memory cell array;
- a decoder circuit for controlling to select the transfer gates for each of the multiple stages in said transfer gate group;
- and
- a plurality of terminals for transmitting signals corresponding to the columns in said memory cell array, wherein one of said plurality of terminals also serves as said external terminal.
4 more elements
A semiconductor memory device comprising:
- a memory cell array that always allows the memory cells to be accessed in parallel;
- decode means capable of selecting a signal corresponding to any one of the memory cells during said parallel accessing;
- and
- a single bus line for transmitting said signal selected by said decode means to the outside of the device.
1 more element
Dependencies are inferred from the claim text.