Cascadable multi-channel network memory with dynamic allocation

#The present invention relates to memories generally and, more particularly, to a cascadable multi-channel memory with dynamic allocation suitable for use in a network environment.

#Buffers are used in a variety of applications where it is desirable to connect devices that are operating at different speeds, transfer rates and/or frequencies. In particular applications, such as a network environment, a number of buffers may have to be implemented for each of a number of separate channels in a particular network system. When first-in first-out (FIFO) buffers are implemented for each channel, the overall expense in increasing the depth of the buffers (i.e., each of the FIFOs) may result in device inefficiency.

#An alternate implementation for a multi-channel memory may be to implement static random access memories (SRAMs) as the data buffers. An SRAM based buffer implementation requires a controller to maintain multiple software linked-lists of the entry stored for each of the channels that are stored in each of the SRAMs. The FIFO implementation also requires an intelligent controller to orchestrate the reading and writing of the channel buffers.

#These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

#FIG. 1 is a block diagram of an overall architecture of the present invention;

#FIG. 2 is a more detailed block diagram showing a number of internal channels of the present invention;

#Referring to FIG. 1, a circuit 10 is shown in accordance with a preferred embodiment of the present invention. The circuit generally comprises a write buffer 12, a RAM array 14 and a read buffer 16. The write buffer 12 generally receives an input data stream (e.g., DataIn) at an input 18. The write buffer generally presents information to the RAM array 14. The read buffer generally retrieves the information from the RAM array 14 and presents the information at an output 20. The output 20 may present an output data stream (e.g., DataOut). The input data stream DataIn and the output data stream DataOut may each be multibit signals that represent various channels of information to be independently stored in the RAM array 14. The write buffer 12 generally presents information to an input 22 of the RAM array 14, while the read buffer 16 generally reads information from an output 24 of the RAM array 14.

#Referring to FIG. 2, a more detailed block diagram of the circuit 10 is shown. The RAM array 14 is shown comprising a number of internal channels (e.g., List1-Listn). The channel List1 may comprise data received at the input 22 that may be stored at a number of cells (or storage elements) 30a-30n. Additional channels may be stored in the List2-Listn that each comprise a number of cells (or storage elements) for storing information. For example, the List2 may comprise a number of cells (or storage elements) 32a-32n, the List7 may comprise a number of cells (or storage elements) 34a-34n, and the Listn generally comprises a number of cells (or storage elements) 36a-36n.

#Each cell has an associated "TAG" entry (to be described in more detail in connection with FIG. 8) which contains the list ID number of the cell, the valid cell bit, and the pointer to the next cell in the same list. The valid cell bit indicates that the cell is currently in use (and therefore not free to be allocated).