Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same

#The present invention relates in general to electronic memories and in particular to a dynamic random access memory system with simultaneous access and refresh operations and methods using the same.

#Dynamic random access memory (DRAM) is the principal type of memory used in most applications such as personal computers (PCS). When compared, for example, to static random access memory (SRAM), DRAM is less expensive, consumes substantially less power, and provides more bits in the same chip space (i.e. has a higher cell density). DRAM is normally used to construct those memory subsystems, such as system memories and display frame buffers, where power conservation and high cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, thus making DRAM the prevalent type of memory device on the market.

#Notwithstanding these significant advantages, DRAMs are also subject to significant restraints due to the manner in which they must be constructed and operated. Specifically, since each cell stores data as charge on a capacitor (i.e. charged to a predetermined voltage for a logic 1 and discharged to approximately 0 volts for a logic 0), the length of time a bit, and in particular a logic 1 bit, can be stored in a given cell is a function of the ability of the capacitor to retain charge. Charge retention, and consequently data integrity is in turn is a function of charge leakage.

#For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

#FIGS. 1A and 1B are block diagrams respectively depicting two basic system architectures typical of those found in personal computers;

#FIG. 2 illustrates a high level functional block diagram of a DRAM memory embodying the principles of the present invention;

#The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1-6 of the drawings, in which like numbers designate like parts.

#FIGS. 1A and 1B are block diagrams respectively depicting two basic system architectures 100A and 100B typical of those found in personal computers (PCS). While numerous variations on these basic architectures exist, FIGS. 1A and 1B are suitable for describing the basic structure and operation of most PCS. Both systems 100A and 100B include a single central processing unit 101, CPU local data bus 102, CPU local address bus 103, external (L2) cache 104, core logic/memory controller 105, and system memory 106. In system 100A, the peripherals 108 are coupled directly to core logic/memory controller 105 via a bus 107. Bus 107 in this case is preferably a peripheral controller interface (PCI) bus, although alternatively it could be an ISA, general, or special purpose bus, as known in the art. In system 100B, core logic/memory controller 105 is again coupled to bus 107. A PCI bus bridge then interfaces bus 107 with a PCI bus 110, to which the peripherals 111 couple. An additional bus 112, which may be a ISA, PCI, VESA, IDE, general, or special purpose bus, is provided for access to peripherals 111 from an external device or system (not shown).

#In single CPU systems 100A and 100B, CPU 101 is the "master" which, in combination with the operating system and applications software, controls the overall operation of system 100. Among other things, CPU 101 performs various data processing functions including numerical and word processing, generates graphics data, and performs overall system management. CPU 101 may be for example a complex instruction set computer (CISC), such as an Intel Pentium.TM. class microprocessor, a reduced instruction set computer (RISC), such as a Apple PowerPC.TM. microprocessor, or a very long instruction word (VLIW) machine.