Sense amplifier with zero power idle mode
AssigneeAtmel Corporation
InventorsSaroj Pathak, Glen A. Rosendale, James E. Payne, Nianglamching Hangzo
Life of this patent
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Abstract
A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
Claims15
In a memory device having an array of memory cells organized as a plurality of N-bit data and having N sense amplifiers, wherein said memory device outputs a bit for each period of a clock signal, wherein each sense amplifier includes a differential amp stage, a reference voltage stage, and a data latch, a method of operating each sense amplifier, comprising:
- (i) generating an enable pulse having a first logic level and a second logic level;
- (ii) in response to said enable pulse being at said first logic level, enabling one of said differential amp stage and said reference voltage stage;
- (iii) after enabling one of said differential amp stage and said reference voltage stage, enabling the other of said differential amp stage and said reference voltage stage;
- and
- (iv) after substep (ii), clearing said data latch and coupling said data latch to an output of said differential amp stage;
- (v) changing said enable pulse to said second logic level;
- and
- (vi) in response to said enable pulse being at said second logic level, latching said output of said differential amp stage;
- (vii) after latching said output, disabling one of said differential amp stage and said reference voltage stage;
- and
- (viii) after disabling one of said differential amp stage and said reference voltage stage, disabling the other of said differential amp stage and said reference voltage stage.
A data sensing circuit for use in a memory device having a plurality of memory cells organized as N-bit data, wherein said data sensing circuit senses the N bits of an accessed memory location and wherein said memory device outputs a bitstream at a rate of one bit per period of a clock signal;
- said data sensing circuit comprising:
- a plurality of sense amplifiers, each sense amplifier including a differential amplifier stage, a reference voltage stage and a data latch;
- pulse means for generating a control pulse every Nth cycle of said clock signal, said control pulse being at a first logic level for a duration of time .DELTA.-t, .DELTA.-t being a period of time sufficient to read out a memory cell, and said control pulse being at a second logic level at all other times;
- control means, coupled to said pulse means and to said sense amplifiers, for enabling said differential amplifier stage prior to enabling said reference voltage stage, and for disabling said differential amplifier stage prior to disabling said reference voltage stage, and
- means for electrically coupling said data latch to an output of said differential amplifier stage, said control means further effective for enabling said coupling means subsequent to enabling said differential amplifier stage and said reference voltage stage, and for disabling said coupling means prior to disabling said differential amplifier stage and said reference voltage stage.
A sense amplifier for use in a memory device having an array of memory cells organized as a plurality of N-bit data and having N such sense amplifiers for simultaneously reading out the N bits of an accessed memory location, wherein said memory device outputs a bit for each period of a clock signal, said sense amplifier comprising:
- a differential amplifier stage, including an input coupled to sense the state of a memory cell;
- a reference voltage stage coupled to provide a reference voltage to said differential amplifier stage;
- a data latch to hold the state of a sensed memory cell:
- timing means for producing a control pulse every N cycles of said clock signal, said control pulse having a pulse width sufficient to allow reading out an accessed memory cell;
- a first circuit to electrically couple said data latch to an output of said differential amplifier stage in the absence of said control pulse, and to electrically decouple said data latch in the presence of said control pulse;
- a second circuit to enable said differential amplifier stage in the presence of said control pulse, and to disable said differential amplifier stage in the absence of said control pulse;
- and
- a third circuit to enable said reference voltage stage in the presence of said control pulse, and to disable said reference voltage stage in the absence of said control pulse.
Dependencies are inferred from the claim text.