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US 5,963,493 AGranted
Memory device communication line control
AssigneeMicron Technology, Inc.
InventorsTodd A. Merritt, Donald M. Morgan
Life of this patent
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Abstract
A memory device is described which equilibrates and precharges the input/output lines synchronously during a write cycle and asynchronously during a read cycle. During a read cycle, the timing of equilibration and precharge functions are decoupled from the clock signal and asynchronously initiate the equilibrate and precharge functions of the I/O lines in response to a latch signal. The invention initiates the equilibration and precharging of the I/O lines earlier in the access cycle thereby increasing memory access speed.
Claims13
A method of operating a memory device comprising:
- performing a first equilibrate and pre-charge operation on input/output data communication lines in response to an externally provided clock signal;
- coupling externally provided data signals to the input/output data communication lines;
- storing the data signals provided on the input/output data communication lines in first memory cells;
- performing second equilibrate and pre-charge operations on the input/output data communication lines in preparation for a new memory cell access operation, the second equilibrate and pre-charge operations are performed in response to the externally provided clock signal;
- accessing second memory cells provided in the memory device;
- coupling data stored in the second memory cells to the input/output data communication lines;
- latching the data on the input/output data communication lines in a latch circuit, the latch circuit is operated in response to an internally generated latch signal;
- and
- pre-charging and equilibrating the input/output data communication lines in response to the latch signal.
6 more elements
A method of operating a memory device comprising:
- initiating a write operation using a processor coupled to the memory device;
- performing a first equilibrate operation on input/output data communication lines in response to an externally provided clock signal;
- performing a first pre-charge operation on the input/output data communication lines in response to the externally provided clock signal;
- storing externally provided data in first memory cells;
- performing second equilibrate and pre-charge operations on the input/output data communication lines in preparation for a new memory cell access operation, the equilibrate and pre-charge operations are performed in response to the externally provided clock signal;
- accessing second memory cells provided in the memory device during a read operation;
- coupling a data stored in the second memory cells to the input/output data communication lines;
- latching the data on the input/output data communication lines in a latch circuit, the latch circuit is operated in response to an internally generated latch signal;
- isolating the input/output data communication lines from the latch circuit in response to the latch signal;
- and
- performing a third pre-charge and equilibrate operation on the input/output data communication lines in response to the latch circuit.
8 more elements
A method of operating a memory device comprising:
- performing equilibrate and pre-charge operations on input/output data communication lines in preparation for a memory cell access operation, the equilibrate and pre-charge operations are performed in response to an externally provided clock signal;
- initiating a read operation using a processor;
- accessing memory cells provided in the memory device during the read operation;
- coupling a data stored in the second memory cells to the input/output data communication lines;
- latching the data on the input/output data communication lines in a latch circuit, the latch circuit is operated in response to an internally generated latch signal;
- and
- pre-charging and equilibrating the input/output data communication lines in response to the latch circuit.
4 more elements
A method of operating a memory device comprising:
- performing equilibrate and pre-charge operations on input/output data communication lines in preparation for a memory cell access operation, the equilibrate and pre-charge operations are performed in response to an externally provided clock signal;
- initiating a read operation using a processor;
- accessing memory cells provided in the memory device during the read operation;
- coupling a data stored in the second memory cells to the input/output data communication lines;
- latching the data on the input/output data communication lines in a first latch circuit, the latch circuit is operated in response to an internally generated latch signal;
- isolating the input/output data communication lines from the latch circuit in response to the latch signal;
- generating a pulse signal in response to the latch signal;
- latching the pulse signal in a second latch circuit;
- pre-charging and equilibrating the input/output data communication lines in response to an output signal from the second latch circuit;
- and
- resetting the output signal from the second latch circuit in response to the externally provided clock signal.
8 more elements
A method of operating a memory device comprising:
- initiating a write operation using a processor coupled to the memory device;
- generating a first pulse signal in response to an externally provided clock signal;
- equilibrating input/output data communication lines in response to the first pulse signal;
- generating a second pulse signal in response to the externally provided clock signal;
- pre-charging the input/output data communication lines in response to the second pulse signal;
- coupling externally provided data signals to the input/output data communication lines;
- accessing first memory cells provided in the memory device;
- storing the data signals provided on the input/output data communication lines in the first memory cells;
- performing equilibrate and pre-charge operations on the input/output data communication lines in preparation for a new memory cell access operation, the equilibrate and pre-charge operations are performed in response to the externally provided clock signal;
- initiating a read operation using the processor;
- accessing second memory cells provided in the memory device during the read operation;
- coupling a charge stored in the second memory cells to digit lines provided in the memory device;
- sensing and amplifying the charge coupled to the digit lines;
- coupling the digit lines to the input/output data communication lines, to couple data to the input/output data communication lines;
- latching the data on the input/output data communication lines in a latch circuit, the latch circuit is operated in response to an internally generated latch signal;
- isolating the input/output data communication lines from the latch circuit in response to the latch signal;
- generating a third pulse signal in response to the latch signal;
- latching the third pulse signal in a second latch circuit;
- pre-charging and equilibrating the input/output data communication lines in response to an output signal from the second latch circuit;
- and
- resetting the output signal from the second latch circuit in response to the externally provided clock signal.
18 more elements
A method of operating a memory device comprising:
- latching data provided on complementary data communication lines using a latch circuit, the latch circuit is activated in response to a latch signal;
- electrically isolating the latch circuit from the complementary data communication lines in response to the latch signal;
- and
- performing a voltage pre-charge operation and a voltage equilibration operation the complementary data communication lines in response to the latch signal.
1 more element
A method of operating a memory device comprising:
- latching data provided on complementary data communication lines using a first latch circuit, the first latch circuit is activated in response to a latch signal;
- electrically isolating the first latch circuit from the complementary data communication lines in response to the latch signal;
- coupling the latch signal to first pulse generator to provide a first output voltage pulse signal in response to the latch signal;
- placing a second latch circuit in a first state in response to the first output voltage pulse signal, such that an output signal from the second latch circuit triggers an equilibration operation, and a pre-charge operation of the complementary data lines;
- receiving a clock signal;
- placing the second latch circuit in a second state in response to the received clock signal;
- and
- triggering a subsequent equilibration and pre-charge operation of the complementary data lines in response to the clock signal.
5 more elements
Dependencies are inferred from the claim text.