Semiconductor memory
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutami Arimoto
Life of this patent
Estimating the term…
Abstract
A semiconductor memory comprising memory cells, a write buffer, a write inversion gate, a data input terminal, and four write data buses 1-4. The write buffer and the write inversion gate place onto two write data buses 1 and 3 the data input through the data input terminal. The inverted data of the input data is output onto two other write data buses 2 and 4. This causes alternately different data to be written to four contiguous memory cells. The scheme permits detection of a cell fault caused by interference between contiguous memory cells.
Claims15
A semiconductor memory having a test mode, comprising:
- a memory array including a plurality of memory cells arranged in matrix fashion;
- selecting means for selecting in said test mode, from said memory array N memory cells, where N is an integer not smaller than 2;
- writing means for generating a second signal by inverting an externally applied first signal, and for writing a first and a second signal in parallel to said N memory cells selected by said selecting means so that, M memory cells among said N memory cells store sad first signal and N-M memory cells store said second signal, where M is an integer not smaller than 1 and smaller than N;
- reading means for reading in parallel N signals from said n memory cells;
- and
- a test circuit for inverting, of N signals read by said reading means, the signal read from the memory cell to which one of said first and second signals is written and for determining that N memory cells are normal when logic of the signal read from the memory cell to which the other signal has been written coincides with the logic of said inverted signal.
A semiconductor memory comprising:
- a memory array;
- a write inversion gate for selectively writing one of first and second data complementary each other into each of a plurality of memory cells included in said memory array;
- a read inversion gate for reading data from the plurality of memory cells and inverting data read from the memory cell to which second data is written;
- and
- a detection circuit for producing a test result in a test mode, the test result indicating whether data read from the memory cell to which first data is written and data inverted by said read inversion gate are in agreement.
Dependencies are inferred from the claim text.