A method of testing a static semiconductor memory device including a plurality of memory cells each having first and second storage nodes to be set at potentials of different levels from each other, comprising the steps of:
- rendering a difference in potential between said first storage nodes and said second storage nodes in a testing mode that is smaller than a difference in potential between said first storage nodes and said second storage nodes in normal use for a memory cell that is to be tested;
- and, during said rendering step:
- flowing current into one of said first storage node and said second storage node in the memory cell to be tested;
- and
- reading data from the memory cell to which said current is flowed.